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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk/llvm-master-aarch64-spec2k6-Os in repository toolchain/ci/llvm-project.
from dec624682e0 [MachineCSE][MachinePRE] Avoid hoisting code from code regi [...] adds 4ccb7f8c450 [AMDGPU][MC] Corrected parsing of branch offsets adds b288d90b39f [NFC] include cstdint/string prior to using uint8_t/string adds cb2c50028d8 lld-link: Demangle symbols from archives in diagnostics adds 5905aae1695 DAG: Handle dbg_value for arguments split into multiple subregs adds 9dc0160d267 [clangd] Disable background-index on lit-tests by default adds c35dd05a7ce gn build: Set +x on symlink_or_copy.py adds 8bb8915d43f [clangd] Provide a way to publish highlightings in non-racy manner adds 1022c0dfde5 AMDGPU: Decompose all values to 32-bit pieces for calling c [...] adds 9e6a42a1856 [libc++] Add missing %link_flags to .sh.cpp test adds 3fd917d8860 Support Linux signal return trampolines in frame initialization adds fecf43eba36 AMDGPU/GlobalISel: Rewrite lowerFormalArguments adds b60a2ae40e7 AMDGPU/GlobalISel: Support arguments with multiple registers adds 08494f6231b AMDGPU/GlobalISel: Selection for fminnum/fmaxnum adds fd8a3651f74 AMDGPU: Attempt to fix bot error adds f41e6271572 [libunwind][ARM] Fix loading FP registers on big-endian targets adds 8e46275488c Fix asan infinite loop on undefined symbol
No new revisions were added by this update.
Summary of changes: clang-tools-extra/clangd/ClangdServer.cpp | 17 +- clang-tools-extra/clangd/TUScheduler.cpp | 60 +- clang-tools-extra/clangd/TUScheduler.h | 20 +- clang-tools-extra/clangd/tool/ClangdMain.cpp | 6 +- .../clangd/unittests/TUSchedulerTests.cpp | 27 +- compiler-rt/lib/interception/interception_linux.cc | 9 +- .../test/asan/TestCases/Linux/dlopen-mixed-c-cxx.c | 42 + .../libcxx/strings/basic.string/PR42676.sh.cpp | 2 +- libunwind/src/Unwind-EHABI.cpp | 9 +- lld/COFF/Driver.cpp | 15 +- lld/COFF/Driver.h | 2 +- lld/COFF/InputFiles.cpp | 9 +- lld/COFF/InputFiles.h | 2 +- lld/COFF/SymbolTable.cpp | 8 +- lld/COFF/SymbolTable.h | 2 +- lld/COFF/Symbols.cpp | 11 +- lld/COFF/Symbols.h | 1 + lld/test/COFF/Inputs/mangled-symbol.s | 9 + lld/test/COFF/thin-archive.s | 36 + lldb/include/lldb/Symbol/UnwindPlan.h | 14 + .../handle-abrt}/Makefile | 0 .../signal/handle-abrt/TestHandleAbort.py | 72 + .../test/functionalities/signal/handle-abrt/main.c | 25 + .../Plugins/ABI/MacOSX-arm/ABIMacOSX_arm.cpp | 1 + .../Plugins/ABI/MacOSX-arm64/ABIMacOSX_arm64.cpp | 1 + .../Plugins/ABI/MacOSX-i386/ABIMacOSX_i386.cpp | 1 + lldb/source/Plugins/ABI/SysV-arm/ABISysV_arm.cpp | 1 + .../Plugins/ABI/SysV-arm64/ABISysV_arm64.cpp | 2 + .../Plugins/ABI/SysV-hexagon/ABISysV_hexagon.cpp | 1 + lldb/source/Plugins/ABI/SysV-i386/ABISysV_i386.cpp | 1 + lldb/source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp | 1 + .../Plugins/ABI/SysV-mips64/ABISysV_mips64.cpp | 1 + lldb/source/Plugins/ABI/SysV-ppc/ABISysV_ppc.cpp | 1 + .../Plugins/ABI/SysV-ppc64/ABISysV_ppc64.cpp | 1 + .../Plugins/ABI/SysV-x86_64/ABISysV_x86_64.cpp | 1 + .../Instruction/ARM/EmulateInstructionARM.cpp | 1 + .../Instruction/ARM64/EmulateInstructionARM64.cpp | 1 + .../Instruction/MIPS/EmulateInstructionMIPS.cpp | 1 + .../MIPS64/EmulateInstructionMIPS64.cpp | 1 + .../Instruction/PPC64/EmulateInstructionPPC64.cpp | 1 + .../Plugins/Platform/Linux/PlatformLinux.cpp | 2 + .../Process/Utility/RegisterContextLLDB.cpp | 34 +- .../SymbolFile/Breakpad/SymbolFileBreakpad.cpp | 1 + .../x86/x86AssemblyInspectionEngine.cpp | 1 + lldb/source/Symbol/ArmUnwindInfo.cpp | 1 + lldb/source/Symbol/CompactUnwindInfo.cpp | 4 + lldb/source/Symbol/DWARFCallFrameInfo.cpp | 4 + .../include/llvm/Demangle/MicrosoftDemangleNodes.h | 2 + .../llvm/Target/GlobalISel/SelectionDAGCompat.td | 4 + .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 75 +- llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp | 488 +++-- llvm/lib/Target/AMDGPU/AMDGPUCallLowering.h | 11 +- llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td | 7 - llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 74 - llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 6 +- .../Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 63 +- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 94 +- llvm/lib/Target/AMDGPU/SIISelLowering.h | 27 + .../AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.mir | 308 +++ .../AMDGPU/GlobalISel/inst-select-fmaxnum.mir | 307 +++ .../AMDGPU/GlobalISel/inst-select-fminnum-ieee.mir | 308 +++ .../AMDGPU/GlobalISel/inst-select-fminnum.mir | 307 +++ .../AMDGPU/GlobalISel/inst-select-maxnum.mir | 60 - .../AMDGPU/GlobalISel/inst-select-minnum.mir | 59 - .../AMDGPU/GlobalISel/irtranslator-amdgpu_ps.ll | 35 +- .../AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll | 16 +- .../GlobalISel/irtranslator-function-args.ll | 1987 ++++++++++++++++++++ .../AMDGPU/GlobalISel/regbankselect-maxnum.mir | 66 - .../AMDGPU/GlobalISel/regbankselect-minnum.mir | 66 - llvm/test/CodeGen/AMDGPU/call-argument-types.ll | 16 +- llvm/test/CodeGen/AMDGPU/debug-value2.ll | 8 +- llvm/test/CodeGen/AMDGPU/implicit-def-muse.ll | 7 +- .../reduce-build-vec-ext-to-ext-build-vec.ll | 6 +- llvm/test/CodeGen/AMDGPU/shift-i128.ll | 201 +- llvm/test/CodeGen/AMDGPU/si-scheduler.ll | 2 +- llvm/test/CodeGen/AMDGPU/split-arg-dbg-value.ll | 224 +++ llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll | 152 +- llvm/test/CodeGen/AMDGPU/wait.ll | 8 +- llvm/test/CodeGen/AMDGPU/wwm-reserved.ll | 6 +- llvm/test/MC/AMDGPU/branch-comment.s | 3 - llvm/test/MC/AMDGPU/sopk.s | 10 + llvm/test/MC/AMDGPU/sopp-err.s | 18 + llvm/test/MC/AMDGPU/sopp.s | 12 + llvm/utils/gn/build/symlink_or_copy.py | 0 84 files changed, 4619 insertions(+), 887 deletions(-) create mode 100644 compiler-rt/test/asan/TestCases/Linux/dlopen-mixed-c-cxx.c create mode 100644 lld/test/COFF/Inputs/mangled-symbol.s create mode 100644 lld/test/COFF/thin-archive.s copy lldb/packages/Python/lldbsuite/test/functionalities/{breakpoint/breakpoint_ig [...] create mode 100644 lldb/packages/Python/lldbsuite/test/functionalities/signal/hand [...] create mode 100644 lldb/packages/Python/lldbsuite/test/functionalities/signal/hand [...] create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.mir delete mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-maxnum.mir delete mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-minnum.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll delete mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-maxnum.mir delete mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-minnum.mir create mode 100644 llvm/test/CodeGen/AMDGPU/split-arg-dbg-value.ll mode change 100644 => 100755 llvm/utils/gn/build/symlink_or_copy.py