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from c4845edfeaf c++: Fix handling of no-linkage decls for modules new d91a0cee361 [PATCH] RISC-V: Add XiangShan Nanhu microarchitecture.
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Summary of changes: gcc/config/riscv/riscv-cores.def | 6 + gcc/config/riscv/riscv-opts.h | 1 + gcc/config/riscv/riscv.cc | 17 +++ gcc/config/riscv/riscv.md | 3 +- gcc/config/riscv/xiangshan.md | 148 +++++++++++++++++++++ .../gcc.target/riscv/mcpu-xiangshan-nanhu.c | 34 +++++ 6 files changed, 208 insertions(+), 1 deletion(-) create mode 100644 gcc/config/riscv/xiangshan.md create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-xiangshan-nanhu.c