This is an automated email from the git hooks/post-receive script.
unknown user pushed a change to branch master in repository llvm.
from 5cd1e6d400d Revert "[MIPS] Add support to match more patterns for DINS [...] new 1f4a80fdc1f Add extra operand to CALLSEQ_START to keep frame part set u [...]
The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.
Summary of changes: include/llvm/CodeGen/ISDOpcodes.h | 7 +++++++ include/llvm/CodeGen/SelectionDAG.h | 12 ++++++++---- include/llvm/Target/TargetInstrInfo.h | 13 ++++++++++++- include/llvm/Target/TargetSelectionDAG.td | 2 +- lib/CodeGen/MachineVerifier.cpp | 4 ++-- lib/CodeGen/SelectionDAG/FastISel.cpp | 2 +- lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 2 +- lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 4 ++-- lib/Target/AArch64/AArch64CallLowering.cpp | 2 +- lib/Target/AArch64/AArch64FastISel.cpp | 2 +- lib/Target/AArch64/AArch64ISelLowering.cpp | 4 +--- lib/Target/AArch64/AArch64InstrInfo.td | 8 +++++--- lib/Target/ARM/ARMBaseInstrInfo.h | 18 ++++-------------- lib/Target/ARM/ARMCallLowering.cpp | 2 +- lib/Target/ARM/ARMFastISel.cpp | 2 +- lib/Target/ARM/ARMISelLowering.cpp | 3 +-- lib/Target/ARM/ARMInstrInfo.td | 7 ++++--- lib/Target/ARM/ARMInstrThumb.td | 4 ++-- lib/Target/AVR/AVRFrameLowering.cpp | 2 +- lib/Target/AVR/AVRISelLowering.cpp | 3 +-- lib/Target/AVR/AVRInstrInfo.td | 6 +++--- lib/Target/BPF/BPFISelLowering.cpp | 3 +-- lib/Target/BPF/BPFInstrInfo.td | 9 +++++---- lib/Target/Hexagon/HexagonISelLowering.cpp | 3 +-- lib/Target/Hexagon/HexagonPatterns.td | 7 ++++--- lib/Target/Hexagon/HexagonPseudo.td | 2 +- lib/Target/Lanai/LanaiISelLowering.cpp | 5 +---- lib/Target/Lanai/LanaiInstrInfo.td | 9 +++++---- lib/Target/MSP430/MSP430FrameLowering.cpp | 7 +++---- lib/Target/MSP430/MSP430ISelLowering.cpp | 3 +-- lib/Target/MSP430/MSP430InstrInfo.h | 6 ++++++ lib/Target/MSP430/MSP430InstrInfo.td | 7 ++++--- lib/Target/Mips/MipsFastISel.cpp | 2 +- lib/Target/Mips/MipsISelLowering.cpp | 2 +- lib/Target/Mips/MipsInstrInfo.td | 6 +++--- lib/Target/NVPTX/NVPTXISelLowering.cpp | 3 +-- lib/Target/NVPTX/NVPTXInstrInfo.td | 9 +++++---- lib/Target/PowerPC/PPCFastISel.cpp | 2 +- lib/Target/PowerPC/PPCISelLowering.cpp | 20 ++++++++------------ lib/Target/PowerPC/PPCInstrInfo.td | 11 +++++++---- lib/Target/PowerPC/PPCTLSDynamicCall.cpp | 3 ++- lib/Target/Sparc/SparcISelLowering.cpp | 8 +++----- lib/Target/Sparc/SparcInstrInfo.td | 9 +++++---- lib/Target/SystemZ/SystemZISelLowering.cpp | 4 +--- lib/Target/SystemZ/SystemZInstrInfo.td | 4 ++-- lib/Target/SystemZ/SystemZOperators.td | 3 ++- lib/Target/WebAssembly/WebAssemblyInstrCall.td | 4 ++-- lib/Target/WebAssembly/WebAssemblyInstrInfo.td | 3 ++- lib/Target/X86/X86FastISel.cpp | 2 +- lib/Target/X86/X86ISelLowering.cpp | 10 +++++----- lib/Target/X86/X86InstrCompiler.td | 14 ++++++++------ lib/Target/X86/X86InstrInfo.h | 7 ++++++- lib/Target/X86/X86InstrInfo.td | 3 ++- lib/Target/XCore/XCoreISelLowering.cpp | 3 +-- lib/Target/XCore/XCoreInstrInfo.td | 11 ++++++----- test/CodeGen/AArch64/GlobalISel/call-translator.ll | 4 ++-- test/CodeGen/AArch64/stackmap-frame-setup.ll | 4 ++-- test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll | 16 ++++++++-------- test/CodeGen/Hexagon/regalloc-bad-undef.mir | 8 ++++---- test/CodeGen/Lanai/peephole-compare.mir | 4 ++-- .../MIR/X86/frame-info-save-restore-points.mir | 2 +- test/CodeGen/PowerPC/stackmap-frame-setup.ll | 4 ++-- test/CodeGen/X86/stackmap-frame-setup.ll | 4 ++-- 63 files changed, 190 insertions(+), 169 deletions(-)