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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu/gnu-master-arm-bootstrap_O1 in repository toolchain/ci/gcc.
from 2d22ab64c47 [AArch32] ACLE intrinsics bfloat16 vmmla and vfma<b/t> for [...] adds 3a0e583bf17 i386: Fix some -O0 avx2intrin.h and xopintrin.h intrinsic m [...] adds 55ace4d1463 Fix location maybe_diag_overlap passes to diagnostics so th [...] adds 8c044c65773 Commit correct version of gimple.c file adds c9d70946b3c c: ignore initializers for elements of variable-size types [...] adds 22a75da901b [PATCH][testuite] Fix pr80481.C after epilogue vectorization adds 34ec7d5347e Daily bump. adds 5358e8f5800 i386: Properly encode vector registers in vector move adds 46275300312 re PR tree-optimization/90883 (Generated code is worse if r [...] adds 655e5c29ae4 Fix error format string. adds 1f520d34129 aarch64: ACLE intrinsics for BFCVTN, BFCVTN2 and BFCVT adds 12007097342 RISC-V: Fix testsuite regression due to recent IRA changes. adds ff229375721 ACLE intrinsics: BFloat16 store (vst<n>{q}_bf16) intrinsics [...] adds eb637e76047 ACLE intrinsics: BFloat16 load intrinsics for AArch32 adds 28119fba7f1 libstdc++: Deal with ENOSYS == ENOTSUP adds 180eeeaeb20 libstdc++: Fix failing filesystem::path tests (PR 93244) adds 068fe0a9e99 Add missing ChangeLog entries adds b0815713a32 libstdc++: Fix call to __glibcxx_rwlock_init (PR 93244) adds 4cdcb2c92a1 libstdc++: Fix PR number in ChangeLog (PR 94069) adds 6d082cd9013 libstdc++: Give ranges::empty() a concrete return type (PR 93978) adds 6aa2ca21a44 libstdc++: Add missing friend declaration to join_view::_Sentinel adds 4b62b3960ec arc: Update tumaddsidi4 test. adds e6ce69cae50 Avoid putting a REG_NOTE on anything other than an INSN in [...] adds 3dcf51ad7b0 rs6000: Correct logic to disable NO_SUM_IN_TOC and NO_FP_IN [...] adds 4a5c938bbfd [AArch64][SVE] Add missing movprfx attribute to some ternar [...] adds 3e5c062e96c [AArch64] Fix lane specifier syntax adds 0b839322117 [AArch64] Use intrinsics for widening multiplies (PR91598) adds 191bcd0f30d Fix mangling ICE [PR94027] adds 41f99ba6c57 analyzer: improvements to state dumping adds 90f7c3007d5 analyzer: improvements to region_model::get_representative_tree adds 2a4c59d9aa6 Daily bump. adds 6733ecaf3fe gcc.target/i386/pr89229-3c.c: Include "pr89229-3a.c" adds ff0a62841e2 c++: Fix pretty printing of TYPENAME_TYPEs adds 5e1b4e60c18 c++: Fix missing SFINAE when binding a bit-field to a refer [...] adds 9de42a8e995 Patch and ChangeLogs for PR93581 adds 0b4ee25bdd7 Daily bump. adds d5114529228 [testsuite] Fix PR94023 to guard case under vect_hw_misalign adds cb2c60206f4 [testsuite] Fix PR94019 to check vector char when vect_hw_misalign adds 016d0f9e43c Insert default return_void at the end of coroutine body adds 2e94d3ee47b alias: Punt after walking too many VALUEs during a toplevel [...] adds 314b91220a0 Restore alignment in rs6000 target. adds 157e23d8803 [testsuite][arm] Fix typo in fuse-caller-save.c adds 8475f2902a2 c++: Fix ABI issue with alignas on armv7hl [PR94050] adds 29b1533acd5 configure - build libgomp by default for amdgcn adds 9439378f7a0 rs6000: Fix -mlong-double documentation adds a931bb50fe7 Fix 'A' operand modifier: PR inline-asm/94095 adds 5dc1390b41d Revert: One more patch for PR93564: Prefer smaller hard reg [...] adds 81fa6d7321d c++: Readd [LR]ROTATE_EXPR support to constexpr.c [PR94067] adds ea182fe6363 libstdc++: Handle type-changing path concatenations (PR 94063) adds d417b4f5414 c++: Fix convert_like in template [PR91465, PR93870, PR9203 [...] adds 406d2cecabd Update cpplib da.po. adds 983a6e7a502 Daily bump. adds 8fc37274021 gdbinit.in: Fix typo. adds c1263058ba0 Update gcc sv.po. adds cc5c935937d i386: Fix up *testqi_ext_3 insn&split for the *testdi_1 cha [...] adds 3654d49d0ff libstdc++: Change compile-only test to run adds c222eabcf8b libstdc++: Fix invalid noexcept-specifier (PR 94117) adds aed151bb53b Revert "Fix regression reported by tester due to recent IRA [...] adds cfd90eb9ed0 testsuite: Scan for SSE reg-reg moves only in pr80481.C adds 90b5ebd7693 minor: fix intendation in ddg.c adds b888a051deb loop-iv: make find_simple_exit static adds cf0c3a45731 libstdc++: Fix noexcept guarantees for ranges::split_view adds e00cb200f39 PR90763: PowerPC vec_xl_len should take const argument. adds 14af5d9b19b c++: Partially revert patch for PR66139. adds b269a014771 c++: Add tests for PR93922 and PR94041. adds 0b7f1e24316 libstdc++: Fix uses of _M_current in split_view's outer iterator adds 76743c8a6ab Daily bump. adds 37e0df8a9be rs6000: Check -+0 and NaN for smax/smin generation adds df15a82804e c++: Fix ICE with omitted template args [PR93956]. adds 481fcfe6fec c++: Fix deferred noexcept on constructor [PR93901]. adds e11d05c1ed2 c++: Fix wrong conversion error with non-viable overload [PR94124] adds 5115542a5cc Fix length computation for movsi_insv which resulted in reg [...] adds 8f0d8cd8522 libstdc++: LWG 3286 ranges::size is not required to be vali [...] adds 05ac4d9c7b3 ldist: Further fixes for -ftrapv [PR94114] adds 312992f5a07 dfp: Fix decimal_to_binary [PR94111] adds 60342fdbfb0 value-prof: Fix abs uses in value-prof.c [PR93962] adds 42bc589e87a aarch64: Fix ICE in aarch64_add_offset_1 [PR94121] adds a5aac267e64 Fix internal error on locally-defined subpools adds e835226bab5 Fix GIMPLE verification failure in LTO mode on Ada code adds d564c5e254d [testsuite] Add @ lines to check-function-bodies fluff adds cb99630f254 fold undefined pointer offsetting adds 5fea87cc790 RISC-V: Fix testsuite regression due to recent IRA changes. adds d42ff1d3b62 pdp11: Fix handling of common (local and global) vars [PR94134] adds 1c43ee69f4f Bug fix: cannot convert 'const short int*' to 'const __bf16*' adds 4512b7d8518 libstdc++: Add a test that takes the split_view of a non-fo [...] adds 7eb5be6ab91 c++: Fix wrong modifying const object error for COMPONENT_R [...] adds bde31a76ba4 c++: Fix ICE with concepts and aliases [PR93907]. adds 923e1785276 Daily bump. adds 690de2b706b testsuite: Fix concepts-using2.C failure on 32-bit targets [...] adds 9c1281d9863 Add myself to MAINTAINERS adds f457ae2218c [rs6000] Fix a wrong GC issue adds aedb4c8fc77 Update myself to MAINTAINERS adds 4069adf4bbc c++: Tweak reshape_init_array_1 [PR94124] adds 349ab34dc64 tree-dse: Fix mem* head trimming if call has lhs [PR94130] adds b73f69020f0 doc: Fix up ASM_OUTPUT_ALIGNED_DECL_LOCAL description adds 98aeb1ef510 [Fortran, OpenACC] Reject vars of different scope in $acc d [...] adds 54f46d82f54 i386: Use ix86_output_ssemov for MMX TYPE_SSEMOV adds fcc443b97e1 libstdc++: Fix test failure due to -Wnonnull warnings adds 1dc00a8ec9a tree-optimization/94103 avoid CSE of loads with padding adds a0ae4cbe9d1 maintainer-scripts: Fix jit documentation build with update [...] adds c56871dd15a maintainer-scripts: Fix up gcc_release without -l, where mk [...] adds daf2852b883 Support for the CPEN control register was removed in rev .5 [...] adds 4aded535ea6 Remove no-op register to register copies in CSE just like w [...] adds 54e69cb00da Daily bump. adds 82f620e2ba4 Fix unaligned load with small memcpy on the ARM adds 3e6ab5cefa8 Fix incorrect filling of delay slots in branchy code at -O2 adds dbf3dc75888 aarch64: Add --params to control the number of recip steps [...] adds fd8679974b2 i386: Use ix86_output_ssemov for DFmode TYPE_SSEMOV adds 7aa605c9d46 aarch64: Fix another bug in aarch64_add_offset_1 [PR94121] adds 43d513af3f2 [testsuite] Fix PR93935 to guard case under vect_hw_misalign adds 98ff89d1ac5 Do not strcat to result of getenv. adds 3604480a6fe tree-optimization/94163 constrain alignment set by PRE adds 80a13af724a c++: Redundant -Wdeprecated-declarations warning in build_o [...] adds 5c7e6d4bdf8 df: Don't abuse bb->aux (PR94148, PR94042) adds 9ae8bc02774 testsuite: Assorted x32 testsuite fixes adds f2e9fe5f97d PR c/94040 - ICE on a call to an invalid redeclaration of strftime adds 3b515f74841 Fix wrong year in ChangeLog. adds 45ee7a35f34 PR c/94040 - ICE on a call to an invalid redeclaration of strftime adds a4504f32c05 PR92303: Try to simplify memory subreg. adds db3fa3476e9 testsuite: Fix misquoted string in bfcvt-nosimd.c adds 5b74dd0a227 d/dmd: Merge upstream dmd e9420cfbf adds 5c048755ec9 analyzer: handle NOP_EXPR in get_lvalue [PR94099,PR94105] adds 50c96067c8e Fix UBSAN error, shifting 64 bit value by 64. adds 0034955eb16 Daily bump. adds 53b28abf8e4 Fix doubled indefinite articles, mostly in comments. adds 9a6408bd18f rs6000/test: Fix selector in fold-vec-mule-misc.c adds 6e5084b4401 libphobos: Merge upstream druntime 7915b6a3 adds c393c99d3dc c++: Fix CTAD with multiple-arg ctor template [93248]. adds b3b0c671cc3 c++: Find parameter pack in typedef in lambda [92909]. adds 3a285529ee3 c++: Fix ICE-after-error on partial spec [92068] adds 824722e45f8 i386: Use ix86_output_ssemov for DImode TYPE_SSEMOV adds 89769d70af2 Daily bump. adds 9c3cdb43c2b tree-nested: Fix handling of *reduction clauses with C arra [...] adds b408e010ccf driver: Fix redundant descriptions in options adds ced66da3135 coroutines: Fix indentation (NFC). adds 9d74caf21be i386: Use ix86_output_ssemov for SFmode TYPE_SSEMOV adds 5e5ce5371f6 Daily bump. adds e4e9a59105a Update post order number for merged SCC. adds 5ba25b2ef17 tree-inline: Fix a -fcompare-debug issue in the inliner [PR94167] adds 6d44c881286 tree-inline: Fix a -fcompare-debug issue in the inliner [PR94167] adds f2d3807f580 libphobos: Merge upstream druntime 6c45dd3a, phobos 68cc18adb. adds e41d4a0a567 d/dmd: Merge upstream dmd b061bd744 adds 5a3c42b227b i386: Use ix86_output_ssemov for SImode TYPE_SSEMOV adds 136fec1e27f x32 does not support MS ABI, skip testcases that require it. adds f19b40bd377 Fix ChangeLog formatting from my commit last friday. adds bc093503d74 libphobos: Reset libtool_VERSION to 1:0:0 adds 63c8f7d6a08 [ARM][GCC][1/x]: MVE ACLE intrinsics framework patch. adds c7be0832b54 [ARM][GCC][2/x]: MVE ACLE intrinsics framework patch. adds 5dee500b359 [ARM][GCC][3/x]: MVE ACLE intrinsics framework patch. adds f522810d2b5 [testsuite] Avoid duplicate test names in sizeless tests adds bae7b38cf8a Fix PR94185: Do not reuse insn alternative after changing m [...] adds c015ff8ccaf c: Handle MEM_REF in c_fully_fold* [PR94179] adds 447d196e75d d: Fix multiple definition error when using mixins and interfaces. adds c62f5e6e1f4 libstdc++: Add default constructor to net::service_already_ [...] adds 2691ffe6dba d: Fix assignment to anonymous union member corrupts siblin [...] adds b3f246f12b2 Daily bump. adds 950183c7741 Update gcc sv.po. adds 57e7ad5a8fd c++: Add test for PR 93901. adds ecf2b69a629 Filter a test-case with gas. adds 7afa3b82918 expand: Don't depend on warning flags in code generation of [...] adds 741ff2a263f strlen: Punt on UB reads past end of string literal [PR94187] adds fd857de8070 c: ignore initializers for elements of variable-size types [...] adds 994d4862062 testsuite: Fix pr94185.C testcase on i686-linux with C++98 [...] adds 14782c8123e [ARM][GCC][4/x]: MVE ACLE vector interleaving store intrinsics. adds a50f6abffc3 [ARM][GCC][1/1x]: Patch to support MVE ACLE intrinsics with [...] adds 5db0eb95c34 [ARM][GCC][2/1x]: MVE intrinsics with unary operand. adds a9a437ffc42 tree-ssa-strlen: Fix up count_nonzero_bytes* [PR94015] adds f582ca0fd70 [GCC][PATCH][ARM] Add multilib mapping for Armv8.1-M+MVE wi [...] adds 700d4cb08c8 Fix up duplicated duplicated words mostly in comments adds 6df4618cac9 [ARM][GCC][3/1x]: MVE intrinsics with unary operand. adds a475f153431 [ARM][GCC][4/1x]: MVE intrinsics with unary operand. adds 4be8cf77026 [ARM][GCC][1/2x]: MVE intrinsics with binary operands. adds 887085be635 c++: Fix access checks for __is_assignable and __is_constructible adds f166a8cdf48 [ARM][GCC][2/2x]: MVE intrinsics with binary operands. adds d71dba7b611 [ARM][GCC][3/2x]: MVE intrinsics with binary operands. adds 33203b4c27d [ARM][GCC][4/2x]: MVE intrinsics with binary operands. adds f9355dee93f [ARM][GCC][5/2x]: MVE intrinsics with binary operands. adds 0dad5b33687 [ARM][GCC][1/3x]: MVE intrinsics with ternary operands. adds e4596b66710 coroutines, testsuite: Fix single test execution. adds 1fef0148be4 Fix the ChangeLog after the __is_assignable/__is_constructible fix adds cf9c3bff39c aarch64: Fix bf16_v(ld|st)n.c failures for big-endian adds 58a703f0726 testsuite: Fix gcc.target/aarch64/advsimd-intrinsics/bfcvt- [...] adds cd0b7124273 c++: Fix parsing of invalid enum specifiers [PR90995] adds 046c58907ec c: Handle C_TYPE_INCOMPLETE_VARS even for ENUMERAL_TYPEs [PR94172] adds 2e30d3e3e88 testsuite: Fix g++.dg/debug/dwarf2/const2b.C target selector adds 3b2cc34369a Daily bump. adds 98f29f5638f libstdc++: Fix type-erasure in experimental::net::executor [...] adds 80616e5b7a5 c++: Fix comment typo. adds 52b3aa8be18 dwarf: Generate DIEs for external variables with -g1 [93751] adds af8656be8df c++: Diagnose a deduction guide in a wrong scope [PR91759] adds 4e3d3e40726 middle-end/94188 fix fold of addr expression generation adds 4da9288745d libgomp testsuite - disable long double for AMDGCN adds cb26919c857 aarch64: Treat p12-p15 as call-preserved in SVE PCS functions adds d91480dee93 aarch64: Fix SYMBOL_TINY_GOT handling for ILP32 [PR94201] adds d5029d45940 Fix up duplicated duplicated words in comments adds 1ba9acb11e3 middle-end/94206 fix memset folding to avoid types with padding adds 11cf25c40e3 PR c++/94147 - mangling of lambdas assigned to globals adds 5a80a6c3e5f amdgcn: Add cond_add/sub/and/ior/xor for all vector modes adds dbde9e2d595 amdgcn: Fix vector compare modes adds 07522ae90b5 libstdc++: Fix compilation with released versions of Clang adds e5de406f996 libstdc++ Fix compilation of <stop_token> with Clang adds 0db2cd17702 analyzer: tweaks to exploded_node ctor adds 7d9c107ab1e analyzer: introduce noop_region_model_context adds f665beeba62 analyzer: add test coverage for fixed ICE [PR94047] adds 884d9141112 analyzer: make summarized dumps more comprehensive adds 26cbcfe5fce Fix libgomp.oacc-fortran/atomic_capture-1.f90 adds 8165795c155 [ARM][GCC][2/3x]: MVE intrinsics with ternary operands. adds e3678b4464a [ARM][GCC][3/3x]: MVE intrinsics with ternary operands. adds db5db9d2548 [ARM][GCC][1/4x]: MVE intrinsics with quaternary operands. adds 8eb3b6b9cf2 [ARM][GCC][2/4x]: MVE intrinsics with quaternary operands. adds f2170a379b0 [ARM][GCC][3/4x]: MVE intrinsics with quaternary operands. adds 532e9e2402a [ARM][GCC][4/4x]: MVE intrinsics with quaternary operands. adds 4ff68575991 [ARM][GCC][1/5x]: MVE store intrinsics. adds 535a8645bb8 [ARM][GCC][2/5x]: MVE load intrinsics. adds 405e918c314 [ARM][GCC][3/5x]: MVE store intrinsics with predicated suffix. adds 429d607bc46 [ARM][GCC][4/5x]: MVE load intrinsics with zero(_z) suffix. adds bf1e3d5afa1 [ARM][GCC][5/5x]: MVE ACLE load intrinsics which load a byt [...] adds 4cc23303bad [ARM][GCC][6/5x]: Remaining MVE load intrinsics which loads [...] adds 5cad47e0f85 [ARM][GCC][7/5x]: MVE store intrinsics which stores byte,ha [...] adds 7a5fffa5ed0 [ARM][GCC][8/5x]: Remaining MVE store intrinsics which stor [...] adds 3512dc0108a PR ipa/92799 - ICE on a weakref function definition followe [...] adds 529ea7d9596 Complete change to resolve pr90275. adds 07fe4af4d51 rs6000: Add back some w* constraints (PR91886) adds b3341826531 libstdc++: Fix is_trivially_constructible (PR 94033) adds b5562f1187d Daily bump. adds 73bc09fa8c6 middle-end/94216 fix another build_fold_addr_expr use adds f3280e4c0c9 ipa/94217 simplify offsetted address build adds c7e90196818 phiopt: Avoid -fcompare-debug bug in phiopt [PR94211] adds bb83e069eba libgomp/testsuite: ignore blank-line output for function-no [...] adds 02f7334ac93 c++: Fix up handling of captured vars in lambdas in OpenMP [...] adds f5389e17e4b Update include/plugin-api.h. adds c8429c2aba8 API extension for binutils (type of symbols). adds f22712bd8a2 Fix inliner ICE on alias with flatten attribute [PR92372] adds 37482edc3f7 d/dmd: Merge upstream dmd d1a606599 adds 9def91e9f2a c: Fix up cfun->function_end_locus from the C FE [PR94029] adds f7dceb4e658 Fix cgraph_node::function_symbol availability compuattion [ [...] adds 3373d3e38ea Daily bump. adds 94e2418780f c++: Avoid unnecessary empty class copy [94175]. adds 4a18f168f47 [rs6000] Rewrite the declaration of a variable adds 05009698eeb gcc, Arm: Fix no_cond issue introduced by MVE adds 4119cd693d2 store-merging: Fix up -fnon-call-exceptions handling [PR94224] adds 0efe7d8796e gcc, Arm: Fix MVE move from GPR -> GPR adds 005f6fc59e5 gcc, Arm: Fix testisms for MVE testsuite adds 719c864225e gcc, Arm: Revert changes to {get,set}_fpscr adds 8fefa21fcf6 tree-optimization/94266 - fix object type extraction heuristics adds 7d4549b2cd2 Fix correct offset in ipa_get_jf_ancestor_result. adds 3eff57aacfe [ARM][GCC][6x]:MVE ACLE vaddq intrinsics using arithmetic p [...] adds 85a94e87901 [ARM][GCC][7x]: MVE vreinterpretq and vuninitializedq intrinsics. adds 92f80065d10 [ARM][GCC][1/8x]: MVE ACLE vidup, vddup, viwdup and vdwdup [...] adds 41e1a7ffae9 [ARM][GCC][2/8x]: MVE ACLE gather load and scatter store in [...] adds 3d42842c07f fix CTOR vectorization adds 261014a1be4 [ARM][GCC][9x]: MVE ACLE predicated intrinsics with (dont-c [...] adds 828878c35c8 c++: Include the constraint parameter mapping in diagnostic [...] adds c3562f81042 [ARM][GCC][10x]: MVE ACLE intrinsics "add with carry across [...] adds 1aa22b1916a c-family: Tighten vector handling in type_for_mode [PR94072] adds b5446d0cc09 d: Fix SEGV in hash_table<odr_name_hasher, false, xcallocat [...] adds 1dfcc3b541c [ARM][GCC][11x]: MVE ACLE vector interleaving store and dei [...] adds a23eff1bd04 c++: Add testcases from PR c++/69694 adds a89349e664f adjust SLP tree dumping adds 72b3bc895f0 Fix verifier ICE on wrong comdat local flag [PR93347] adds 68dd57808f7 rs6000: Add command line and builtin compatibility check adds cc3afc9db07 Regenerate gcc.pot. adds 29f23ed79b6 sra: Cap number of sub-access propagations with a param (PR 93435) adds 8416602026d Daily bump. adds 15711e837b2 Fix comma at end of enumerator list seen with -std=c++98. adds 497498c878d lra: Tighten check for reloading paradoxical subregs [PR94052] adds b599bf9d6d1 c++: Reject changing active member of union during initiali [...] adds 98eb7b2ed24 d: Fix ICE in add_symbol_to_partition_1, at lto/lto-partiti [...] adds 837cece888f Darwin: Address translation comments (PR93694). adds dfb25dfe3d3 Darwin: Handle NULL DECL_SIZE_TYPE in machopic_select_secti [...] adds 9fc985118d9 libstdc++: Fix path::generic_string allocator handling (PR 94242) adds a577c0c2693 libstdc++: Fix experimental::path::generic_string (PR 93245) adds 424e39081f9 d: Fix typo in ChangeLog for last change adds 4a01f7b1e73 d: Fix missing dependencies in depfile for imported files ( [...] adds 88d7d0ce8fa testsuite: Fix lambda-vis.C for targets with user label pre [...] adds 85e10e4f0fa Darwin: Fix i686 bootstrap when the assembler supports GOTO [...] adds fbe60463bb8 d: Generate phony targets for content imported files (PR93038) adds 83aa5aa313a Daily bump. adds 6e00d8dcf32 Daily bump. adds b809f0b6580 Set proper DECL_ALIGN in offload_handle_link_vars (PR94233) adds 2fa4b1ffd6e Save ref->speculative_id before clone_reference. adds 263ee1260bc tree-optimization/94266 - aovid propagating addresses of TA [...] adds 7a2090b04e5 ipa/94245 - avoid folding when we want an ADDR_EXPR adds 26b3e568a60 [PR94044] Fix ICE with sizeof<argumentpack> adds a3586eeb884 AMDGCN offloading – use amdgcn-amdhsa adds ce6413087de lto/lto.c – used $ or . in generated linkptr name adds 4897bb0045d libgomp – fix declare target link handling (PR94251) adds b0d84ecc55f fortran: ICE in gfc_match_assignment PR93600 adds 4dcc4502f31 tree-optimization/94261 - avoid IL adjustments in SLP analysis adds 6debbff6ca3 arm: Add earlyclobber to MVE instructions that require it adds 962406639c0 testsuite, arm: Change tests to assemble adds 0cd55f9d3af libgccjit: handle long literals in playback::context::new_s [...] adds 1a5c27b1b43 [ARM][GCC][12x]: MVE ACLE intrinsics to set and get vector lane. adds 85244449104 [ARM][GCC][13x]: MVE ACLE scalar shift intrinsics. adds 88c9a831f3a [ARM][GCC][14x]: MVE ACLE whole vector left shift with carr [...] adds d326e9586b4 driver: Improve the generated help text for alias options adds 5db9e89323c c: Fix up cfun->function_end_locus on invalid function bodi [...] adds ca6c722561c c++: Handle COMPOUND_EXPRs in get_narrower and warnings_for [...] adds 1f6c1c82eb5 c++: Avoid a suspicious -Wnoexcept warning [PR93805] adds 75fb811dfaa Verify the code used for the optimized comparison is valid [...] adds c86c99e6950 Update gcc es.po, sv.po. adds 75c24a08d69 Daily bump. adds 047811579f0 cgraphunit: Avoid code generation differences based on -w/T [...] adds a5a9400a846 if-conv: Fix -fcompare-debug bugs in ifcvt_local_dce [PR94283] adds 565ab7efbdc loop-manip: Avoid -fcompare-debug issues in create_iv [PR94285] adds 596c90d3559 arm: Fix arm {,u}subvdi4 and usubvsi4 expanders [PR94286] adds 906b3eb9df6 Improve endianess detection. adds c2211a60ff0 Fix OpenMP offload handling for target-link variables for n [...] adds 04099157691 Define __BIG_ENDIAN__ adds 8001f59c82b [testsuite,arm] target-supports.exp: Add arm_fp_dp_ok effec [...] adds 2a0eaca3e9c [testsuite,arm] cmp-2.c: Move double-precision tests to cmp-3.c adds 07f8bcc6ea9 [testsuite,arm] use arm_fp_dp_ok effective-target adds 6e771c087b1 c++: Give more expressions locations. adds 5c161741843 c++: Fix template parm with dependent type in concepts. adds fddfd3ce555 c++: Improve handling of ill-formed constraints [PR94186]. adds 75b7b7fdc45 c++: Fix wrong no post-decrement operator error in template [...] adds 0c1c8d9f137 Daily bump. adds adaf4b6c66e Test for sigsetjmp support in analyzer tests requiring that [...]
No new revisions were added by this update.
Summary of changes: ChangeLog | 5 + MAINTAINERS | 1 + configure | 2 +- configure.ac | 2 +- gcc/ChangeLog | 8177 ++++++ gcc/DATESTAMP | 2 +- gcc/ada/ChangeLog | 5 + gcc/ada/gcc-interface/decl.c | 9 +- gcc/alias.c | 3 + gcc/analyzer/ChangeLog | 111 + gcc/analyzer/analyzer.h | 9 +- gcc/analyzer/diagnostic-manager.cc | 7 +- gcc/analyzer/engine.cc | 15 +- gcc/analyzer/exploded-graph.h | 7 +- gcc/analyzer/program-state.cc | 174 +- gcc/analyzer/program-state.h | 3 +- gcc/analyzer/region-model.cc | 372 +- gcc/analyzer/region-model.h | 93 +- gcc/analyzer/sm-malloc.cc | 2 +- gcc/analyzer/sm.cc | 15 + gcc/analyzer/sm.h | 2 + gcc/asan.c | 7 +- gcc/builtins.c | 22 +- gcc/c-family/ChangeLog | 22 + gcc/c-family/c-common.c | 13 +- gcc/c-family/c-warn.c | 5 + gcc/c-family/c.opt | 22 +- gcc/c/ChangeLog | 60 + gcc/c/c-decl.c | 120 +- gcc/c/c-fold.c | 9 + gcc/c/c-parser.c | 52 +- gcc/c/c-tree.h | 14 +- gcc/c/c-typeck.c | 25 +- gcc/cfgexpand.c | 2 +- gcc/cfgloop.h | 1 - gcc/cgraph.c | 90 +- gcc/cgraph.h | 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+ .../gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpcsq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpcsq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c | 22 + .../arm/mve/intrinsics/vcmpeqq_m_n_f16.c | 22 + .../arm/mve/intrinsics/vcmpeqq_m_n_f32.c | 22 + .../arm/mve/intrinsics/vcmpeqq_m_n_s16.c | 22 + .../arm/mve/intrinsics/vcmpeqq_m_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c | 22 + .../arm/mve/intrinsics/vcmpeqq_m_n_u16.c | 22 + .../arm/mve/intrinsics/vcmpeqq_m_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c | 22 + 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| 21 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c | 22 + .../arm/mve/intrinsics/vcmpgeq_m_n_f16.c | 22 + .../arm/mve/intrinsics/vcmpgeq_m_n_f32.c | 22 + .../arm/mve/intrinsics/vcmpgeq_m_n_s16.c | 22 + .../arm/mve/intrinsics/vcmpgeq_m_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_s32.c | 21 + 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+ .../gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c | 23 + .../arm/mve/intrinsics/vcmulq_rot180_f16.c | 21 + .../arm/mve/intrinsics/vcmulq_rot180_f32.c | 21 + .../arm/mve/intrinsics/vcmulq_rot180_m_f16.c | 23 + .../arm/mve/intrinsics/vcmulq_rot180_m_f32.c | 23 + .../arm/mve/intrinsics/vcmulq_rot180_x_f16.c | 22 + .../arm/mve/intrinsics/vcmulq_rot180_x_f32.c | 22 + .../arm/mve/intrinsics/vcmulq_rot270_f16.c | 21 + .../arm/mve/intrinsics/vcmulq_rot270_f32.c | 21 + .../arm/mve/intrinsics/vcmulq_rot270_m_f16.c | 23 + .../arm/mve/intrinsics/vcmulq_rot270_m_f32.c | 23 + .../arm/mve/intrinsics/vcmulq_rot270_x_f16.c | 22 + .../arm/mve/intrinsics/vcmulq_rot270_x_f32.c | 22 + .../arm/mve/intrinsics/vcmulq_rot90_f16.c | 21 + .../arm/mve/intrinsics/vcmulq_rot90_f32.c | 21 + .../arm/mve/intrinsics/vcmulq_rot90_m_f16.c | 23 + .../arm/mve/intrinsics/vcmulq_rot90_m_f32.c | 23 + .../arm/mve/intrinsics/vcmulq_rot90_x_f16.c | 23 + .../arm/mve/intrinsics/vcmulq_rot90_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcreateq_f16.c | 13 + .../gcc.target/arm/mve/intrinsics/vcreateq_f32.c | 13 + .../gcc.target/arm/mve/intrinsics/vcreateq_s16.c | 13 + .../gcc.target/arm/mve/intrinsics/vcreateq_s32.c | 13 + .../gcc.target/arm/mve/intrinsics/vcreateq_s64.c | 13 + .../gcc.target/arm/mve/intrinsics/vcreateq_s8.c | 13 + .../gcc.target/arm/mve/intrinsics/vcreateq_u16.c | 13 + .../gcc.target/arm/mve/intrinsics/vcreateq_u32.c | 13 + .../gcc.target/arm/mve/intrinsics/vcreateq_u64.c | 13 + .../gcc.target/arm/mve/intrinsics/vcreateq_u8.c | 13 + .../gcc.target/arm/mve/intrinsics/vctp16q.c | 21 + .../gcc.target/arm/mve/intrinsics/vctp16q_m.c | 22 + .../gcc.target/arm/mve/intrinsics/vctp32q.c | 21 + .../gcc.target/arm/mve/intrinsics/vctp32q_m.c | 22 + .../gcc.target/arm/mve/intrinsics/vctp64q.c | 21 + .../gcc.target/arm/mve/intrinsics/vctp64q_m.c | 22 + .../gcc.target/arm/mve/intrinsics/vctp8q.c | 21 + .../gcc.target/arm/mve/intrinsics/vctp8q_m.c | 22 + .../arm/mve/intrinsics/vcvtaq_m_s16_f16.c | 22 + .../arm/mve/intrinsics/vcvtaq_m_s32_f32.c | 22 + .../arm/mve/intrinsics/vcvtaq_m_u16_f16.c | 22 + .../arm/mve/intrinsics/vcvtaq_m_u32_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c | 13 + .../gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c | 13 + .../gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c | 13 + .../gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c | 13 + .../arm/mve/intrinsics/vcvtaq_x_s16_f16.c | 14 + .../arm/mve/intrinsics/vcvtaq_x_s32_f32.c | 14 + .../arm/mve/intrinsics/vcvtaq_x_u16_f16.c | 14 + .../arm/mve/intrinsics/vcvtaq_x_u32_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c | 13 + .../gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c | 13 + .../arm/mve/intrinsics/vcvtbq_m_f16_f32.c | 22 + .../arm/mve/intrinsics/vcvtbq_m_f32_f16.c | 22 + .../arm/mve/intrinsics/vcvtbq_x_f32_f16.c | 14 + .../arm/mve/intrinsics/vcvtmq_m_s16_f16.c | 22 + .../arm/mve/intrinsics/vcvtmq_m_s32_f32.c | 22 + .../arm/mve/intrinsics/vcvtmq_m_u16_f16.c | 22 + .../arm/mve/intrinsics/vcvtmq_m_u32_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c | 13 + .../gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c | 13 + .../gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c | 13 + .../gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c | 13 + .../arm/mve/intrinsics/vcvtmq_x_s16_f16.c | 14 + .../arm/mve/intrinsics/vcvtmq_x_s32_f32.c | 14 + .../arm/mve/intrinsics/vcvtmq_x_u16_f16.c | 14 + .../arm/mve/intrinsics/vcvtmq_x_u32_f32.c | 14 + .../arm/mve/intrinsics/vcvtnq_m_s16_f16.c | 22 + .../arm/mve/intrinsics/vcvtnq_m_s32_f32.c | 22 + .../arm/mve/intrinsics/vcvtnq_m_u16_f16.c | 22 + .../arm/mve/intrinsics/vcvtnq_m_u32_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c | 13 + .../gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c | 13 + .../gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c | 13 + .../arm/mve/intrinsics/vcvtnq_x_s16_f16.c | 14 + .../arm/mve/intrinsics/vcvtnq_x_s32_f32.c | 14 + .../arm/mve/intrinsics/vcvtnq_x_u16_f16.c | 14 + .../arm/mve/intrinsics/vcvtnq_x_u32_f32.c | 14 + .../arm/mve/intrinsics/vcvtpq_m_s16_f16.c | 22 + .../arm/mve/intrinsics/vcvtpq_m_s32_f32.c | 22 + .../arm/mve/intrinsics/vcvtpq_m_u16_f16.c | 22 + .../arm/mve/intrinsics/vcvtpq_m_u32_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c | 13 + .../gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c | 13 + .../gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c | 13 + .../gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c | 13 + .../arm/mve/intrinsics/vcvtpq_x_s16_f16.c | 14 + .../arm/mve/intrinsics/vcvtpq_x_s32_f32.c | 14 + .../arm/mve/intrinsics/vcvtpq_x_u16_f16.c | 14 + .../arm/mve/intrinsics/vcvtpq_x_u32_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c | 13 + .../gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c | 13 + .../gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c | 13 + .../gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c | 13 + .../arm/mve/intrinsics/vcvtq_m_f16_s16.c | 22 + .../arm/mve/intrinsics/vcvtq_m_f16_u16.c | 22 + .../arm/mve/intrinsics/vcvtq_m_f32_s32.c | 22 + .../arm/mve/intrinsics/vcvtq_m_f32_u32.c | 22 + .../arm/mve/intrinsics/vcvtq_m_n_f16_s16.c | 23 + .../arm/mve/intrinsics/vcvtq_m_n_f16_u16.c | 23 + .../arm/mve/intrinsics/vcvtq_m_n_f32_s32.c | 23 + .../arm/mve/intrinsics/vcvtq_m_n_f32_u32.c | 23 + .../arm/mve/intrinsics/vcvtq_m_n_s16_f16.c | 23 + .../arm/mve/intrinsics/vcvtq_m_n_s32_f32.c | 23 + .../arm/mve/intrinsics/vcvtq_m_n_u16_f16.c | 23 + .../arm/mve/intrinsics/vcvtq_m_n_u32_f32.c | 23 + .../arm/mve/intrinsics/vcvtq_m_s16_f16.c | 22 + .../arm/mve/intrinsics/vcvtq_m_s32_f32.c | 22 + .../arm/mve/intrinsics/vcvtq_m_u16_f16.c | 22 + .../arm/mve/intrinsics/vcvtq_m_u32_f32.c | 22 + .../arm/mve/intrinsics/vcvtq_n_f16_s16.c | 21 + .../arm/mve/intrinsics/vcvtq_n_f16_u16.c | 21 + .../arm/mve/intrinsics/vcvtq_n_f32_s32.c | 21 + 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.../arm/mve/intrinsics/vcvtq_x_n_u16_f16.c | 14 + .../arm/mve/intrinsics/vcvtq_x_n_u32_f32.c | 14 + .../arm/mve/intrinsics/vcvtq_x_s16_f16.c | 14 + .../arm/mve/intrinsics/vcvtq_x_s32_f32.c | 14 + .../arm/mve/intrinsics/vcvtq_x_u16_f16.c | 14 + .../arm/mve/intrinsics/vcvtq_x_u32_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvttq_f16_f32.c | 13 + .../gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c | 13 + .../arm/mve/intrinsics/vcvttq_m_f16_f32.c | 22 + .../arm/mve/intrinsics/vcvttq_m_f32_f16.c | 22 + .../arm/mve/intrinsics/vcvttq_x_f32_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c | 23 + .../arm/mve/intrinsics/vddupq_m_wb_u16.c | 23 + .../arm/mve/intrinsics/vddupq_m_wb_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vddupq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vddupq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vddupq_n_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c | 23 + .../arm/mve/intrinsics/vddupq_x_wb_u16.c | 25 + .../arm/mve/intrinsics/vddupq_x_wb_u32.c | 25 + .../gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c | 25 + .../gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vdupq_n_f16.c | 13 + .../gcc.target/arm/mve/intrinsics/vdupq_n_f32.c | 13 + .../gcc.target/arm/mve/intrinsics/vdupq_n_s16.c | 13 + .../gcc.target/arm/mve/intrinsics/vdupq_n_s32.c | 13 + .../gcc.target/arm/mve/intrinsics/vdupq_n_s8.c | 13 + .../gcc.target/arm/mve/intrinsics/vdupq_n_u16.c | 13 + .../gcc.target/arm/mve/intrinsics/vdupq_n_u32.c | 13 + .../gcc.target/arm/mve/intrinsics/vdupq_n_u8.c | 13 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c | 14 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c | 14 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c | 14 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c | 14 + .../arm/mve/intrinsics/vdwdupq_m_n_u16.c | 23 + .../arm/mve/intrinsics/vdwdupq_m_n_u32.c | 23 + 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| 23 + .../gcc.target/arm/mve/intrinsics/veorq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/veorq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/veorq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/veorq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/veorq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/veorq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/veorq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/veorq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/veorq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/veorq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/veorq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/veorq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/veorq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/veorq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/veorq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/veorq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/veorq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/veorq_x_s8.c | 23 + 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.../gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c | 22 + .../arm/mve/intrinsics/vhcaddq_rot270_m_s16.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot270_m_s32.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot270_m_s8.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot270_s16.c | 21 + .../arm/mve/intrinsics/vhcaddq_rot270_s32.c | 21 + .../arm/mve/intrinsics/vhcaddq_rot270_s8.c | 21 + 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.../gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c | 23 + .../arm/mve/intrinsics/vidupq_m_wb_u16.c | 23 + .../arm/mve/intrinsics/vidupq_m_wb_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vidupq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vidupq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vidupq_n_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c | 23 + .../arm/mve/intrinsics/vidupq_x_wb_u16.c | 25 + .../arm/mve/intrinsics/vidupq_x_wb_u32.c | 25 + .../gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c | 25 + .../arm/mve/intrinsics/viwdupq_m_n_u16.c | 23 + .../arm/mve/intrinsics/viwdupq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c | 23 + .../arm/mve/intrinsics/viwdupq_m_wb_u16.c | 23 + .../arm/mve/intrinsics/viwdupq_m_wb_u32.c | 23 + .../arm/mve/intrinsics/viwdupq_m_wb_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c | 21 + .../arm/mve/intrinsics/viwdupq_x_n_u16.c | 23 + .../arm/mve/intrinsics/viwdupq_x_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c | 23 + .../arm/mve/intrinsics/viwdupq_x_wb_u16.c | 23 + .../arm/mve/intrinsics/viwdupq_x_wb_u32.c | 23 + .../arm/mve/intrinsics/viwdupq_x_wb_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vld1q_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vld1q_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vld1q_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vld1q_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vld1q_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vld1q_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vld1q_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vld1q_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vld1q_z_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vld1q_z_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vld1q_z_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vld1q_z_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vld1q_z_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vld1q_z_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vld1q_z_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vld1q_z_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vld2q_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vld2q_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vld2q_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vld2q_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vld2q_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vld2q_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vld2q_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vld2q_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vld4q_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vld4q_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vld4q_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vld4q_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vld4q_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vld4q_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vld4q_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vld4q_u8.c | 24 + .../arm/mve/intrinsics/vldrbq_gather_offset_s16.c | 21 + .../arm/mve/intrinsics/vldrbq_gather_offset_s32.c | 21 + .../arm/mve/intrinsics/vldrbq_gather_offset_s8.c | 21 + .../arm/mve/intrinsics/vldrbq_gather_offset_u16.c | 21 + .../arm/mve/intrinsics/vldrbq_gather_offset_u32.c | 21 + .../arm/mve/intrinsics/vldrbq_gather_offset_u8.c | 21 + .../mve/intrinsics/vldrbq_gather_offset_z_s16.c | 21 + .../mve/intrinsics/vldrbq_gather_offset_z_s32.c | 21 + .../arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c | 21 + .../mve/intrinsics/vldrbq_gather_offset_z_u16.c | 21 + .../mve/intrinsics/vldrbq_gather_offset_z_u32.c | 21 + .../arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vldrbq_s16.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrbq_s32.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrbq_s8.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrbq_u16.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrbq_u32.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrbq_u8.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c | 13 + .../arm/mve/intrinsics/vldrdq_gather_base_s64.c | 13 + .../arm/mve/intrinsics/vldrdq_gather_base_u64.c | 13 + .../arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c | 13 + .../arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c | 13 + .../mve/intrinsics/vldrdq_gather_base_wb_z_s64.c | 11 + .../mve/intrinsics/vldrdq_gather_base_wb_z_u64.c | 11 + .../arm/mve/intrinsics/vldrdq_gather_base_z_s64.c | 13 + .../arm/mve/intrinsics/vldrdq_gather_base_z_u64.c | 13 + .../arm/mve/intrinsics/vldrdq_gather_offset_s64.c | 21 + .../arm/mve/intrinsics/vldrdq_gather_offset_u64.c | 21 + .../mve/intrinsics/vldrdq_gather_offset_z_s64.c | 21 + .../mve/intrinsics/vldrdq_gather_offset_z_u64.c | 21 + .../intrinsics/vldrdq_gather_shifted_offset_s64.c | 21 + .../intrinsics/vldrdq_gather_shifted_offset_u64.c | 21 + .../vldrdq_gather_shifted_offset_z_s64.c | 21 + .../vldrdq_gather_shifted_offset_z_u64.c | 21 + .../gcc.target/arm/mve/intrinsics/vldrhq_f16.c | 13 + .../arm/mve/intrinsics/vldrhq_gather_offset_f16.c | 21 + .../arm/mve/intrinsics/vldrhq_gather_offset_s16.c | 21 + .../arm/mve/intrinsics/vldrhq_gather_offset_s32.c | 21 + .../arm/mve/intrinsics/vldrhq_gather_offset_u16.c | 21 + .../arm/mve/intrinsics/vldrhq_gather_offset_u32.c | 21 + .../mve/intrinsics/vldrhq_gather_offset_z_f16.c | 21 + .../mve/intrinsics/vldrhq_gather_offset_z_s16.c | 21 + .../mve/intrinsics/vldrhq_gather_offset_z_s32.c | 21 + .../mve/intrinsics/vldrhq_gather_offset_z_u16.c | 21 + .../mve/intrinsics/vldrhq_gather_offset_z_u32.c | 21 + .../intrinsics/vldrhq_gather_shifted_offset_f16.c | 21 + .../intrinsics/vldrhq_gather_shifted_offset_s16.c | 21 + .../intrinsics/vldrhq_gather_shifted_offset_s32.c | 21 + .../intrinsics/vldrhq_gather_shifted_offset_u16.c | 21 + .../intrinsics/vldrhq_gather_shifted_offset_u32.c | 21 + .../vldrhq_gather_shifted_offset_z_f16.c | 21 + .../vldrhq_gather_shifted_offset_z_s16.c | 21 + .../vldrhq_gather_shifted_offset_z_s32.c | 21 + .../vldrhq_gather_shifted_offset_z_u16.c | 21 + .../vldrhq_gather_shifted_offset_z_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vldrhq_s16.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrhq_s32.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrhq_u16.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrhq_u32.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrwq_f32.c | 13 + .../arm/mve/intrinsics/vldrwq_gather_base_f32.c | 13 + .../arm/mve/intrinsics/vldrwq_gather_base_s32.c | 13 + .../arm/mve/intrinsics/vldrwq_gather_base_u32.c | 13 + .../arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c | 13 + .../arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c | 13 + .../arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c | 13 + .../mve/intrinsics/vldrwq_gather_base_wb_z_f32.c | 13 + .../mve/intrinsics/vldrwq_gather_base_wb_z_s32.c | 13 + .../mve/intrinsics/vldrwq_gather_base_wb_z_u32.c | 13 + .../arm/mve/intrinsics/vldrwq_gather_base_z_f32.c | 13 + .../arm/mve/intrinsics/vldrwq_gather_base_z_s32.c | 13 + .../arm/mve/intrinsics/vldrwq_gather_base_z_u32.c | 13 + .../arm/mve/intrinsics/vldrwq_gather_offset_f32.c | 21 + .../arm/mve/intrinsics/vldrwq_gather_offset_s32.c | 21 + .../arm/mve/intrinsics/vldrwq_gather_offset_u32.c | 21 + .../mve/intrinsics/vldrwq_gather_offset_z_f32.c | 21 + .../mve/intrinsics/vldrwq_gather_offset_z_s32.c | 21 + .../mve/intrinsics/vldrwq_gather_offset_z_u32.c | 21 + .../intrinsics/vldrwq_gather_shifted_offset_f32.c | 21 + .../intrinsics/vldrwq_gather_shifted_offset_s32.c | 21 + .../intrinsics/vldrwq_gather_shifted_offset_u32.c | 21 + .../vldrwq_gather_shifted_offset_z_f32.c | 21 + .../vldrwq_gather_shifted_offset_z_s32.c | 21 + .../vldrwq_gather_shifted_offset_z_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vldrwq_s32.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrwq_u32.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c | 13 + .../gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxaq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxaq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxaq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxavq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxavq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxavq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c | 21 + .../arm/mve/intrinsics/vmaxnmavq_p_f16.c | 21 + .../arm/mve/intrinsics/vmaxnmavq_p_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxvq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxvq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxvq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxvq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxvq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxvq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vminaq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminaq_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminaq_m_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vminaq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vminaq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vminaq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vminavq_p_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vminavq_p_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vminavq_p_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vminavq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vminavq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vminavq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vminnmaq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vminnmaq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmavq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vminnmavq_f32.c | 21 + .../arm/mve/intrinsics/vminnmavq_p_f16.c | 21 + .../arm/mve/intrinsics/vminnmavq_p_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vminnmq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vminnmq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmvq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vminnmvq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vminq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vminq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vminq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vminq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vminq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vminq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vminq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vminq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vminq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vminq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vminq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vminq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vminq_x_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminq_x_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminq_x_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vminq_x_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminq_x_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminq_x_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_p_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vminvq_p_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vminvq_p_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vminvq_p_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vminvq_p_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vminvq_p_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vminvq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vminvq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vminvq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vminvq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vminvq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vminvq_u8.c | 21 + .../arm/mve/intrinsics/vmladavaq_p_s16.c | 22 + .../arm/mve/intrinsics/vmladavaq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c | 22 + .../arm/mve/intrinsics/vmladavaq_p_u16.c | 22 + .../arm/mve/intrinsics/vmladavaq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavaq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavaq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavaq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavaq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavaq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavaq_u8.c | 21 + .../arm/mve/intrinsics/vmladavaxq_p_s16.c | 22 + .../arm/mve/intrinsics/vmladavaxq_p_s32.c | 22 + .../arm/mve/intrinsics/vmladavaxq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavaxq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavaxq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavaxq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavq_u8.c | 21 + .../arm/mve/intrinsics/vmladavxq_p_s16.c | 21 + .../arm/mve/intrinsics/vmladavxq_p_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavxq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavxq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavxq_s8.c | 21 + .../arm/mve/intrinsics/vmlaldavaq_p_s16.c | 21 + .../arm/mve/intrinsics/vmlaldavaq_p_s32.c | 21 + .../arm/mve/intrinsics/vmlaldavaq_p_u16.c | 21 + .../arm/mve/intrinsics/vmlaldavaq_p_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c | 21 + .../arm/mve/intrinsics/vmlaldavaxq_p_s16.c | 21 + .../arm/mve/intrinsics/vmlaldavaxq_p_s32.c | 21 + .../arm/mve/intrinsics/vmlaldavaxq_p_u16.c | 21 + .../arm/mve/intrinsics/vmlaldavaxq_p_u32.c | 21 + .../arm/mve/intrinsics/vmlaldavaxq_s16.c | 21 + .../arm/mve/intrinsics/vmlaldavaxq_s32.c | 21 + .../arm/mve/intrinsics/vmlaldavq_p_s16.c | 21 + .../arm/mve/intrinsics/vmlaldavq_p_s32.c | 21 + .../arm/mve/intrinsics/vmlaldavq_p_u16.c | 21 + .../arm/mve/intrinsics/vmlaldavq_p_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c | 21 + .../arm/mve/intrinsics/vmlaldavxq_p_s16.c | 21 + .../arm/mve/intrinsics/vmlaldavxq_p_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlasq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlasq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlasq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlasq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlasq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlasq_n_u8.c | 21 + .../arm/mve/intrinsics/vmlsdavaq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlsdavaq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c | 21 + .../arm/mve/intrinsics/vmlsdavaxq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlsdavaxq_p_s32.c | 22 + .../arm/mve/intrinsics/vmlsdavaxq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsdavq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsdavq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsdavq_s8.c | 21 + .../arm/mve/intrinsics/vmlsdavxq_p_s16.c | 21 + .../arm/mve/intrinsics/vmlsdavxq_p_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsdavxq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsdavxq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsdavxq_s8.c | 21 + .../arm/mve/intrinsics/vmlsldavaq_p_s16.c | 21 + .../arm/mve/intrinsics/vmlsldavaq_p_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c | 21 + .../arm/mve/intrinsics/vmlsldavaxq_p_s16.c | 21 + .../arm/mve/intrinsics/vmlsldavaxq_p_s32.c | 21 + .../arm/mve/intrinsics/vmlsldavaxq_s16.c | 21 + .../arm/mve/intrinsics/vmlsldavaxq_s32.c | 21 + .../arm/mve/intrinsics/vmlsldavq_p_s16.c | 21 + .../arm/mve/intrinsics/vmlsldavq_p_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c | 21 + .../arm/mve/intrinsics/vmlsldavxq_p_s16.c | 21 + .../arm/mve/intrinsics/vmlsldavxq_p_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovlbq_s16.c | 21 + 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+ .../gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovnbq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmovnbq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmovnbq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmovnbq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovntq_m_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovntq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmovntq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmovntq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmovntq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmulhq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulhq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulhq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulhq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulhq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulhq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulhq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmulhq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmulhq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmulhq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmulhq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmulhq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmulhq_x_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulhq_x_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulhq_x_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulhq_x_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulhq_x_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulhq_x_u8.c | 22 + .../arm/mve/intrinsics/vmullbq_int_m_s16.c | 23 + .../arm/mve/intrinsics/vmullbq_int_m_s32.c | 23 + .../arm/mve/intrinsics/vmullbq_int_m_s8.c | 23 + .../arm/mve/intrinsics/vmullbq_int_m_u16.c | 23 + .../arm/mve/intrinsics/vmullbq_int_m_u32.c | 23 + .../arm/mve/intrinsics/vmullbq_int_m_u8.c | 23 + .../arm/mve/intrinsics/vmullbq_int_s16.c | 21 + .../arm/mve/intrinsics/vmullbq_int_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmullbq_int_s8.c | 21 + .../arm/mve/intrinsics/vmullbq_int_u16.c | 21 + .../arm/mve/intrinsics/vmullbq_int_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmullbq_int_u8.c | 21 + .../arm/mve/intrinsics/vmullbq_int_x_s16.c | 22 + .../arm/mve/intrinsics/vmullbq_int_x_s32.c | 22 + .../arm/mve/intrinsics/vmullbq_int_x_s8.c | 22 + .../arm/mve/intrinsics/vmullbq_int_x_u16.c | 22 + .../arm/mve/intrinsics/vmullbq_int_x_u32.c | 22 + .../arm/mve/intrinsics/vmullbq_int_x_u8.c | 22 + .../arm/mve/intrinsics/vmullbq_poly_m_p16.c | 23 + .../arm/mve/intrinsics/vmullbq_poly_m_p8.c | 23 + .../arm/mve/intrinsics/vmullbq_poly_p16.c | 21 + .../arm/mve/intrinsics/vmullbq_poly_p8.c | 21 + .../arm/mve/intrinsics/vmullbq_poly_x_p16.c | 22 + .../arm/mve/intrinsics/vmullbq_poly_x_p8.c | 22 + .../arm/mve/intrinsics/vmulltq_int_m_s16.c | 23 + .../arm/mve/intrinsics/vmulltq_int_m_s32.c | 23 + .../arm/mve/intrinsics/vmulltq_int_m_s8.c | 23 + .../arm/mve/intrinsics/vmulltq_int_m_u16.c | 23 + .../arm/mve/intrinsics/vmulltq_int_m_u32.c | 23 + .../arm/mve/intrinsics/vmulltq_int_m_u8.c | 23 + .../arm/mve/intrinsics/vmulltq_int_s16.c | 21 + .../arm/mve/intrinsics/vmulltq_int_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmulltq_int_s8.c | 21 + .../arm/mve/intrinsics/vmulltq_int_u16.c | 21 + .../arm/mve/intrinsics/vmulltq_int_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmulltq_int_u8.c | 21 + .../arm/mve/intrinsics/vmulltq_int_x_s16.c | 22 + .../arm/mve/intrinsics/vmulltq_int_x_s32.c | 22 + .../arm/mve/intrinsics/vmulltq_int_x_s8.c | 22 + .../arm/mve/intrinsics/vmulltq_int_x_u16.c | 22 + .../arm/mve/intrinsics/vmulltq_int_x_u32.c | 22 + .../arm/mve/intrinsics/vmulltq_int_x_u8.c | 22 + .../arm/mve/intrinsics/vmulltq_poly_m_p16.c | 23 + .../arm/mve/intrinsics/vmulltq_poly_m_p8.c | 23 + .../arm/mve/intrinsics/vmulltq_poly_p16.c | 21 + .../arm/mve/intrinsics/vmulltq_poly_p8.c | 21 + .../arm/mve/intrinsics/vmulltq_poly_x_p16.c | 22 + .../arm/mve/intrinsics/vmulltq_poly_x_p8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmulq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmulq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c | 23 + 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.../gcc.target/arm/mve/intrinsics/vnegq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vnegq_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vnegq_m_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vnegq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vnegq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vnegq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vnegq_x_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vnegq_x_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vnegq_x_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vnegq_x_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vnegq_x_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vornq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vornq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vornq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_m_s8.c | 23 + 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.../gcc.target/arm/mve/intrinsics/vorrq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vorrq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_m_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vorrq_m_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vorrq_m_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vorrq_m_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vorrq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_n_s16.c | 13 + .../gcc.target/arm/mve/intrinsics/vorrq_n_s32.c | 13 + .../gcc.target/arm/mve/intrinsics/vorrq_n_u16.c | 13 + .../gcc.target/arm/mve/intrinsics/vorrq_n_u32.c | 13 + .../gcc.target/arm/mve/intrinsics/vorrq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vorrq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vorrq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vorrq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vorrq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vorrq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vorrq_x_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vorrq_x_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vorrq_x_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vorrq_x_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vorrq_x_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vorrq_x_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vorrq_x_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vorrq_x_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vpnot.c | 21 + .../gcc.target/arm/mve/intrinsics/vpselq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vpselq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vpselq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vpselq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vpselq_s64.c | 21 + .../gcc.target/arm/mve/intrinsics/vpselq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vpselq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vpselq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vpselq_u64.c | 21 + .../gcc.target/arm/mve/intrinsics/vpselq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vqabsq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqabsq_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqabsq_m_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqabsq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqabsq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqabsq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vqaddq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqaddq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqaddq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vqaddq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqaddq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqaddq_u8.c | 21 + .../arm/mve/intrinsics/vqdmladhq_m_s16.c | 23 + .../arm/mve/intrinsics/vqdmladhq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqdmladhq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqdmladhq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqdmladhq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqdmladhq_s8.c | 21 + .../arm/mve/intrinsics/vqdmladhxq_m_s16.c | 23 + .../arm/mve/intrinsics/vqdmladhxq_m_s32.c | 23 + .../arm/mve/intrinsics/vqdmladhxq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqdmladhxq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqdmladhxq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqdmladhxq_s8.c | 21 + .../arm/mve/intrinsics/vqdmlahq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vqdmlahq_m_n_s32.c | 23 + .../arm/mve/intrinsics/vqdmlahq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqdmlahq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqdmlahq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqdmlahq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vqdmlahq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqdmlahq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqdmlahq_n_u8.c | 21 + .../arm/mve/intrinsics/vqdmlsdhq_m_s16.c | 23 + .../arm/mve/intrinsics/vqdmlsdhq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqdmlsdhq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqdmlsdhq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqdmlsdhq_s8.c | 21 + .../arm/mve/intrinsics/vqdmlsdhxq_m_s16.c | 23 + .../arm/mve/intrinsics/vqdmlsdhxq_m_s32.c | 23 + .../arm/mve/intrinsics/vqdmlsdhxq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s8.c | 21 + .../arm/mve/intrinsics/vqdmulhq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vqdmulhq_m_n_s32.c | 23 + .../arm/mve/intrinsics/vqdmulhq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vqdmulhq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqdmulhq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqdmulhq_s8.c | 21 + .../arm/mve/intrinsics/vqdmullbq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vqdmullbq_m_n_s32.c | 23 + .../arm/mve/intrinsics/vqdmullbq_m_s16.c | 23 + .../arm/mve/intrinsics/vqdmullbq_m_s32.c | 23 + .../arm/mve/intrinsics/vqdmullbq_n_s16.c | 21 + .../arm/mve/intrinsics/vqdmullbq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqdmullbq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqdmullbq_s32.c | 21 + .../arm/mve/intrinsics/vqdmulltq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vqdmulltq_m_n_s32.c | 23 + .../arm/mve/intrinsics/vqdmulltq_m_s16.c | 23 + .../arm/mve/intrinsics/vqdmulltq_m_s32.c | 23 + .../arm/mve/intrinsics/vqdmulltq_n_s16.c | 21 + .../arm/mve/intrinsics/vqdmulltq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqdmulltq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqdmulltq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqmovnbq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovnbq_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovnbq_m_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovnbq_m_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqmovntq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovntq_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovntq_m_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovntq_m_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovntq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqmovntq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqmovntq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqmovntq_u32.c | 21 + .../arm/mve/intrinsics/vqmovunbq_m_s16.c | 22 + .../arm/mve/intrinsics/vqmovunbq_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c | 21 + .../arm/mve/intrinsics/vqmovuntq_m_s16.c | 22 + .../arm/mve/intrinsics/vqmovuntq_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqnegq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqnegq_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqnegq_m_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqnegq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqnegq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqnegq_s8.c | 21 + .../arm/mve/intrinsics/vqrdmladhq_m_s16.c | 23 + .../arm/mve/intrinsics/vqrdmladhq_m_s32.c | 23 + .../arm/mve/intrinsics/vqrdmladhq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c | 21 + .../arm/mve/intrinsics/vqrdmladhxq_m_s16.c | 23 + .../arm/mve/intrinsics/vqrdmladhxq_m_s32.c | 23 + .../arm/mve/intrinsics/vqrdmladhxq_m_s8.c | 23 + .../arm/mve/intrinsics/vqrdmladhxq_s16.c | 21 + .../arm/mve/intrinsics/vqrdmladhxq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c | 21 + .../arm/mve/intrinsics/vqrdmlahq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vqrdmlahq_m_n_s32.c | 23 + .../arm/mve/intrinsics/vqrdmlahq_m_n_s8.c | 23 + .../arm/mve/intrinsics/vqrdmlahq_n_s16.c | 21 + .../arm/mve/intrinsics/vqrdmlahq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c | 21 + .../arm/mve/intrinsics/vqrdmlahq_n_u16.c | 21 + .../arm/mve/intrinsics/vqrdmlahq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u8.c | 21 + .../arm/mve/intrinsics/vqrdmlashq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vqrdmlashq_m_n_s32.c | 23 + .../arm/mve/intrinsics/vqrdmlashq_m_n_s8.c | 23 + .../arm/mve/intrinsics/vqrdmlashq_n_s16.c | 21 + .../arm/mve/intrinsics/vqrdmlashq_n_s32.c | 21 + .../arm/mve/intrinsics/vqrdmlashq_n_s8.c | 21 + .../arm/mve/intrinsics/vqrdmlashq_n_u16.c | 21 + .../arm/mve/intrinsics/vqrdmlashq_n_u32.c | 21 + .../arm/mve/intrinsics/vqrdmlashq_n_u8.c | 21 + .../arm/mve/intrinsics/vqrdmlsdhq_m_s16.c | 23 + .../arm/mve/intrinsics/vqrdmlsdhq_m_s32.c | 23 + .../arm/mve/intrinsics/vqrdmlsdhq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c | 21 + .../arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c | 23 + .../arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c | 23 + .../arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c | 23 + .../arm/mve/intrinsics/vqrdmlsdhxq_s16.c | 21 + .../arm/mve/intrinsics/vqrdmlsdhxq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c | 21 + .../arm/mve/intrinsics/vqrdmulhq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vqrdmulhq_m_n_s32.c | 23 + .../arm/mve/intrinsics/vqrdmulhq_m_n_s8.c | 23 + .../arm/mve/intrinsics/vqrdmulhq_m_s16.c | 23 + .../arm/mve/intrinsics/vqrdmulhq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c | 23 + .../arm/mve/intrinsics/vqrdmulhq_n_s16.c | 21 + .../arm/mve/intrinsics/vqrdmulhq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c | 21 + .../arm/mve/intrinsics/vqrshlq_m_n_s16.c | 22 + .../arm/mve/intrinsics/vqrshlq_m_n_s32.c | 22 + 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+ .../gcc.target/arm/mve/intrinsics/vqrshlq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vqrshlq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqrshlq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqrshlq_u8.c | 21 + .../arm/mve/intrinsics/vqrshrnbq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vqrshrnbq_m_n_s32.c | 23 + .../arm/mve/intrinsics/vqrshrnbq_m_n_u16.c | 23 + .../arm/mve/intrinsics/vqrshrnbq_m_n_u32.c | 23 + .../arm/mve/intrinsics/vqrshrnbq_n_s16.c | 21 + .../arm/mve/intrinsics/vqrshrnbq_n_s32.c | 21 + .../arm/mve/intrinsics/vqrshrnbq_n_u16.c | 21 + .../arm/mve/intrinsics/vqrshrnbq_n_u32.c | 21 + .../arm/mve/intrinsics/vqrshrntq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vqrshrntq_m_n_s32.c | 23 + .../arm/mve/intrinsics/vqrshrntq_m_n_u16.c | 23 + .../arm/mve/intrinsics/vqrshrntq_m_n_u32.c | 23 + .../arm/mve/intrinsics/vqrshrntq_n_s16.c | 21 + .../arm/mve/intrinsics/vqrshrntq_n_s32.c | 21 + .../arm/mve/intrinsics/vqrshrntq_n_u16.c | 21 + .../arm/mve/intrinsics/vqrshrntq_n_u32.c | 21 + .../arm/mve/intrinsics/vqrshrunbq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vqrshrunbq_m_n_s32.c | 23 + .../arm/mve/intrinsics/vqrshrunbq_n_s16.c | 21 + .../arm/mve/intrinsics/vqrshrunbq_n_s32.c | 21 + .../arm/mve/intrinsics/vqrshruntq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vqrshruntq_m_n_s32.c | 23 + .../arm/mve/intrinsics/vqrshruntq_n_s16.c | 21 + .../arm/mve/intrinsics/vqrshruntq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_r_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_r_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_r_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_r_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_r_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_r_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqshlq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshlq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshlq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshlq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshlq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshlq_n_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshlq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshlq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshlq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshlq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshlq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshlq_u8.c | 21 + .../arm/mve/intrinsics/vqshluq_m_n_s16.c | 22 + .../arm/mve/intrinsics/vqshluq_m_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c | 21 + .../arm/mve/intrinsics/vqshrnbq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vqshrnbq_m_n_s32.c | 23 + .../arm/mve/intrinsics/vqshrnbq_m_n_u16.c | 23 + .../arm/mve/intrinsics/vqshrnbq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqshrnbq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshrnbq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshrnbq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshrnbq_n_u32.c | 21 + .../arm/mve/intrinsics/vqshrntq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vqshrntq_m_n_s32.c | 23 + .../arm/mve/intrinsics/vqshrntq_m_n_u16.c | 23 + .../arm/mve/intrinsics/vqshrntq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqshrntq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshrntq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshrntq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshrntq_n_u32.c | 21 + .../arm/mve/intrinsics/vqshrunbq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vqshrunbq_m_n_s32.c | 23 + .../arm/mve/intrinsics/vqshrunbq_n_s16.c | 21 + .../arm/mve/intrinsics/vqshrunbq_n_s32.c | 21 + .../arm/mve/intrinsics/vqshruntq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vqshruntq_m_n_s32.c | 23 + .../arm/mve/intrinsics/vqshruntq_n_s16.c | 21 + .../arm/mve/intrinsics/vqshruntq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vqsubq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqsubq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqsubq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vqsubq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqsubq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqsubq_u8.c | 21 + .../arm/mve/intrinsics/vreinterpretq_f16.c | 44 + .../arm/mve/intrinsics/vreinterpretq_f32.c | 44 + .../arm/mve/intrinsics/vreinterpretq_s16.c | 44 + .../arm/mve/intrinsics/vreinterpretq_s32.c | 44 + .../arm/mve/intrinsics/vreinterpretq_s64.c | 45 + .../arm/mve/intrinsics/vreinterpretq_s8.c | 44 + .../arm/mve/intrinsics/vreinterpretq_u16.c | 44 + .../arm/mve/intrinsics/vreinterpretq_u32.c | 44 + .../arm/mve/intrinsics/vreinterpretq_u64.c | 45 + .../arm/mve/intrinsics/vreinterpretq_u8.c | 44 + .../gcc.target/arm/mve/intrinsics/vrev16q_m_s8.c | 22 + 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+ .../gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_f16.c | 13 + .../gcc.target/arm/mve/intrinsics/vrev64q_f32.c | 13 + .../gcc.target/arm/mve/intrinsics/vrev64q_m_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_m_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_m_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_m_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_m_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_m_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vrev64q_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vrev64q_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vrev64q_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vrev64q_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vrev64q_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrhaddq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vrhaddq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vrhaddq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vrhaddq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vrhaddq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vrhaddq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c | 22 + .../arm/mve/intrinsics/vrmlaldavhaq_p_s32.c | 21 + .../arm/mve/intrinsics/vrmlaldavhaq_p_u32.c | 21 + .../arm/mve/intrinsics/vrmlaldavhaq_s32.c | 21 + .../arm/mve/intrinsics/vrmlaldavhaq_u32.c | 21 + .../arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c | 21 + .../arm/mve/intrinsics/vrmlaldavhaxq_s32.c | 21 + .../arm/mve/intrinsics/vrmlaldavhq_p_s32.c | 21 + .../arm/mve/intrinsics/vrmlaldavhq_p_u32.c | 21 + .../arm/mve/intrinsics/vrmlaldavhq_s32.c | 21 + .../arm/mve/intrinsics/vrmlaldavhq_u32.c | 21 + .../arm/mve/intrinsics/vrmlaldavhxq_p_s32.c | 21 + .../arm/mve/intrinsics/vrmlaldavhxq_s32.c | 21 + .../arm/mve/intrinsics/vrmlsldavhaq_p_s32.c | 21 + .../arm/mve/intrinsics/vrmlsldavhaq_s32.c | 21 + .../arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c | 21 + .../arm/mve/intrinsics/vrmlsldavhaxq_s32.c | 21 + .../arm/mve/intrinsics/vrmlsldavhq_p_s32.c | 21 + .../arm/mve/intrinsics/vrmlsldavhq_s32.c | 21 + .../arm/mve/intrinsics/vrmlsldavhxq_p_s32.c | 21 + .../arm/mve/intrinsics/vrmlsldavhxq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrmulhq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vrmulhq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vrmulhq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vrmulhq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vrmulhq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vrmulhq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrndaq_f16.c | 13 + .../gcc.target/arm/mve/intrinsics/vrndaq_f32.c | 13 + .../gcc.target/arm/mve/intrinsics/vrndaq_m_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrndmq_f16.c | 13 + .../gcc.target/arm/mve/intrinsics/vrndmq_f32.c | 13 + .../gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrndnq_f16.c | 13 + .../gcc.target/arm/mve/intrinsics/vrndnq_f32.c | 13 + .../gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrndpq_f16.c | 13 + .../gcc.target/arm/mve/intrinsics/vrndpq_f32.c | 13 + .../gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrndq_f16.c | 13 + .../gcc.target/arm/mve/intrinsics/vrndq_f32.c | 13 + .../gcc.target/arm/mve/intrinsics/vrndq_m_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrndq_m_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrndq_x_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrndq_x_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrndxq_f16.c | 13 + .../gcc.target/arm/mve/intrinsics/vrndxq_f32.c | 13 + .../gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshlq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshlq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshlq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshlq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshlq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshlq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c | 22 + .../arm/mve/intrinsics/vrshrnbq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vrshrnbq_m_n_s32.c | 23 + .../arm/mve/intrinsics/vrshrnbq_m_n_u16.c | 23 + .../arm/mve/intrinsics/vrshrnbq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c | 21 + .../arm/mve/intrinsics/vrshrntq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vrshrntq_m_n_s32.c | 23 + .../arm/mve/intrinsics/vrshrntq_m_n_u16.c | 23 + .../arm/mve/intrinsics/vrshrntq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vsbciq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vsbciq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vsbcq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vsbcq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c | 15 + .../gcc.target/arm/mve/intrinsics/vshlcq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlcq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlcq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlcq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlcq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlcq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlcq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlcq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlcq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlcq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlcq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlcq_u8.c | 21 + .../arm/mve/intrinsics/vshllbq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c | 23 + .../arm/mve/intrinsics/vshllbq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c | 21 + .../arm/mve/intrinsics/vshllbq_x_n_s16.c | 15 + .../gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c | 15 + .../arm/mve/intrinsics/vshllbq_x_n_u16.c | 15 + .../gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c | 15 + .../arm/mve/intrinsics/vshlltq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c | 23 + .../arm/mve/intrinsics/vshlltq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c | 21 + .../arm/mve/intrinsics/vshlltq_x_n_s16.c | 15 + .../gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c | 15 + .../arm/mve/intrinsics/vshlltq_x_n_u16.c | 15 + .../gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c | 15 + .../gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_m_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_m_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_m_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_m_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlq_n_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlq_r_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlq_r_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlq_r_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlq_r_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlq_r_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlq_r_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c | 15 + .../gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c | 15 + .../gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c | 15 + .../gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c | 15 + .../gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c | 15 + .../gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c | 15 + .../gcc.target/arm/mve/intrinsics/vshlq_x_s16.c | 15 + .../gcc.target/arm/mve/intrinsics/vshlq_x_s32.c | 15 + .../gcc.target/arm/mve/intrinsics/vshlq_x_s8.c | 15 + .../gcc.target/arm/mve/intrinsics/vshlq_x_u16.c | 15 + .../gcc.target/arm/mve/intrinsics/vshlq_x_u32.c | 15 + .../gcc.target/arm/mve/intrinsics/vshlq_x_u8.c | 15 + .../arm/mve/intrinsics/vshrnbq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vshrnbq_m_n_s32.c | 23 + .../arm/mve/intrinsics/vshrnbq_m_n_u16.c | 23 + .../arm/mve/intrinsics/vshrnbq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c | 21 + .../arm/mve/intrinsics/vshrntq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vshrntq_m_n_s32.c | 23 + .../arm/mve/intrinsics/vshrntq_m_n_u16.c | 23 + .../arm/mve/intrinsics/vshrntq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vshrntq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vshrntq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vshrntq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c | 23 + 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s16.c create mode 100644 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f16.c create mode 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create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u8.c create mode 100644 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s16.c create mode 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u32.c create mode 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create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s8.c create mode 100644 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c create mode 100644 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c create mode 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s8.c create mode 100644 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u16.c create mode 100644 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c create mode 100644 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create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u16.c create mode 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u8.c create mode 100644 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s16.c create mode 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpnot.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s8.c create mode 100644 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create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c create mode 100644 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s16.c create mode 100644 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create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_f32.c create mode 100644 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mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u16.c create mode 100644 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mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s8.c create mode 100644 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create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c create mode 100644 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create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u16.c create mode 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c create mode 100644 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gcc/testsuite/gcc.target/i386/pr89229-7b.c create mode 100644 gcc/testsuite/gcc.target/i386/pr89229-7c.c create mode 100644 gcc/testsuite/gcc.target/i386/pr89346.c create mode 100644 gcc/testsuite/gcc.target/i386/pr94088.c create mode 100644 gcc/testsuite/gcc.target/i386/pr94103.c create mode 100644 gcc/testsuite/gcc.target/i386/pr94283.c create mode 100644 gcc/testsuite/gcc.target/powerpc/p9-minmax-3.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pr90763.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pr93800.c create mode 100644 gcc/testsuite/gdc.dg/asm5.d create mode 100644 gcc/testsuite/gdc.dg/fileimports/pr93038.txt create mode 100644 gcc/testsuite/gdc.dg/imports/pr92216.d create mode 100644 gcc/testsuite/gdc.dg/pr92216.d create mode 100644 gcc/testsuite/gdc.dg/pr92309.d create mode 100644 gcc/testsuite/gdc.dg/pr93038.d create mode 100644 gcc/testsuite/gdc.dg/pr93038b.d create mode 100644 gcc/testsuite/gdc.test/compilable/b12001.d create mode 100644 gcc/testsuite/gdc.test/compilable/imports/pr9471a.d create mode 100644 gcc/testsuite/gdc.test/compilable/imports/pr9471b.d create mode 100644 gcc/testsuite/gdc.test/compilable/imports/pr9471c.d create mode 100644 gcc/testsuite/gdc.test/compilable/imports/pr9471d.d create mode 100644 gcc/testsuite/gdc.test/compilable/pr9471.d create mode 100644 gcc/testsuite/gdc.test/compilable/staticforeach.d create mode 100644 gcc/testsuite/gdc.test/compilable/test17819.d create mode 100644 gcc/testsuite/gdc.test/compilable/test18871.d create mode 100644 gcc/testsuite/gdc.test/compilable/test7815.d create mode 100644 gcc/testsuite/gdc.test/compilable/test7886.d create mode 100644 gcc/testsuite/gdc.test/fail_compilation/e7804_1.d create mode 100644 gcc/testsuite/gdc.test/fail_compilation/e7804_2.d delete mode 100644 gcc/testsuite/gdc.test/fail_compilation/fail11169.d create mode 100644 gcc/testsuite/gdc.test/fail_compilation/fail19182.d create mode 100644 gcc/testsuite/gdc.test/fail_compilation/fail19336.d create mode 100644 gcc/testsuite/gdc.test/fail_compilation/fail19520.d create mode 100644 gcc/testsuite/gdc.test/fail_compilation/fail2195.d delete mode 100644 gcc/testsuite/gdc.test/fail_compilation/fail7815.d delete mode 100644 gcc/testsuite/gdc.test/fail_compilation/fail7886.d create mode 100644 gcc/testsuite/gdc.test/fail_compilation/staticforeach1.d create mode 100644 gcc/testsuite/gdc.test/fail_compilation/staticforeach2.d create mode 100644 gcc/testsuite/gdc.test/fail_compilation/staticforeach3.d create mode 100644 gcc/testsuite/gdc.test/fail_compilation/test17307.d create mode 100644 gcc/testsuite/gdc.test/fail_compilation/traits_alone.d create mode 100644 gcc/testsuite/gdc.test/runnable/e7804.d create mode 100644 gcc/testsuite/gdc.test/runnable/staticforeach.d create mode 100644 gcc/testsuite/gfortran.dg/goacc/pr94120-1.f90 create mode 100644 gcc/testsuite/gfortran.dg/goacc/pr94120-2.f90 create mode 100644 gcc/testsuite/gfortran.dg/goacc/pr94120-3.f90 create mode 100644 gcc/testsuite/gfortran.dg/inquiry_type_ref_6.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr93365.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr93600_1.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr93600_2.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr94285.f90 create mode 100644 gcc/testsuite/gnat.dg/subpools1.adb create mode 100644 gcc/testsuite/jit.dg/test-long-string-literal.c create mode 100644 libgomp/testsuite/libgomp.c++/pr93931.C create mode 100644 libgomp/testsuite/libgomp.c/pr93566.c create mode 100644 libstdc++-v3/testsuite/20_util/is_nothrow_constructible/94003.cc create mode 100644 libstdc++-v3/testsuite/27_io/filesystem/path/concat/94063.cc create mode 100644 libstdc++-v3/testsuite/27_io/filesystem/path/generic/94242.cc create mode 100644 libstdc++-v3/testsuite/30_threads/shared_timed_mutex/94069.cc create mode 100644 libstdc++-v3/testsuite/experimental/net/execution_context/make_ [...] create mode 100644 libstdc++-v3/testsuite/experimental/net/executor/1.cc create mode 100644 libstdc++-v3/testsuite/std/ranges/adaptors/93978.cc create mode 100644 libstdc++-v3/testsuite/std/ranges/adaptors/lwg3286.cc create mode 100644 libstdc++-v3/testsuite/std/ranges/subrange/lwg3286.cc