[Tcwg-commits] [toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-mainline-allnoconfig updated (5fda40b28f -> 68b007788a)

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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-mainline-allnoconfig in repository toolchain/ci/binutils-gdb.

from 5fda40b28f gas: make [248]byte directives available everywhere adds 3624a6c15c PR26539, memory leak in inflate.c adds 37a9c3a53e sim: testsuite: allow tests to declare expected exit status adds 7cf91a2481 sim: m32r: clean up redundant test coverage adds 89bfc2a429 sim: frv: clean up redundant test coverage adds 137d6efd8a sim: mips: delete empty stub test dir adds 29fd199ed8 sim: d10v: relocate tests & clean up test harness adds bb3eddb5bd sim: testsuite: delete configure script adds dcd709e056 RISC-V: Comments tidy and improvement. adds b800637e76 RISC-V: Error and warning messages tidy. adds 1942a04836 RISC-V: Indent and GNU coding standards tidy, also aligned t [...] adds 4bb5732e27 RISC-V: Fixed the indent that caused by the previous commits [...] adds 10f92414d6 [gdb/testsuite] Fix gdb.fortran/array-slices.exp with -m32 adds 5a11fff005 gdb/tui: compare pointer to nullptr, not 0 adds e403a898b5 Automatic date update in version.in adds 1368b914e9 sim: testsuite: flatten tree adds eb6e6af8c1 PR26002 undefined symbol VER_NDX_GLOBAL vs. VER_NDX_LOCAL adds ad92f33d38 Tidy inflateEnd calls adds 68b007788a ld/x86: Add -z report-relative-reloc

No new revisions were added by this update.

Summary of changes: bfd/ChangeLog | 45 + bfd/compress.c | 3 +- bfd/elf-linker-x86.h | 3 + bfd/elf32-i386.c | 36 + bfd/elf64-x86-64.c | 33 + bfd/elflink.c | 2 +- bfd/elfnn-riscv.c | 319 +- bfd/elfxx-riscv.c | 54 +- bfd/elfxx-riscv.h | 4 +- bfd/elfxx-x86.c | 47 + bfd/elfxx-x86.h | 4 + bfd/version.h | 2 +- binutils/ChangeLog | 9 + binutils/readelf.c | 8 +- gas/ChangeLog | 23 + gas/config/tc-riscv.c | 521 ++-- gas/config/tc-riscv.h | 6 +- gas/testsuite/gas/riscv/priv-reg-fail-fext.l | 6 +- .../gas/riscv/priv-reg-fail-read-only-01.l | 136 +- .../gas/riscv/priv-reg-fail-read-only-02.l | 48 +- gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l | 130 +- .../gas/riscv/priv-reg-fail-version-1p10.l | 48 +- .../gas/riscv/priv-reg-fail-version-1p11.l | 46 +- .../gas/riscv/priv-reg-fail-version-1p9p1.l | 54 +- gdb/ChangeLog | 4 + gdb/testsuite/ChangeLog | 6 + gdb/testsuite/gdb.fortran/array-slices.exp | 2 +- gdb/tui/tui.c | 4 +- include/ChangeLog | 11 + include/elf/riscv.h | 3 +- include/opcode/riscv-opc.h | 16 +- include/opcode/riscv.h | 127 +- ld/ChangeLog | 35 + ld/NEWS | 3 + ld/emulparams/elf32_x86_64.sh | 1 + ld/emulparams/elf_i386.sh | 1 + ld/emulparams/elf_x86_64.sh | 1 + ld/emulparams/x86-report-relative.sh | 11 + ld/ld.texi | 4 + ld/testsuite/ld-elfvers/vers16.dsym | 2 +- ld/testsuite/ld-elfvers/vers6.dsym | 2 +- ld/testsuite/ld-i386/i386.exp | 1 + ld/testsuite/ld-i386/report-reloc-1.d | 10 + ld/testsuite/ld-i386/report-reloc-1.l | 2 + ld/testsuite/ld-i386/report-reloc-1.s | 12 + .../ld-riscv-elf/attr-merge-priv-spec-failed-01.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-02.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-03.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-04.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-05.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-06.d | 4 +- ld/testsuite/ld-x86-64/report-reloc-1-x32.d | 10 + ld/testsuite/ld-x86-64/report-reloc-1.d | 10 + ld/testsuite/ld-x86-64/report-reloc-1.l | 2 + ld/testsuite/ld-x86-64/report-reloc-1.s | 12 + ld/testsuite/ld-x86-64/x86-64.exp | 2 + opcodes/ChangeLog | 16 + opcodes/riscv-dis.c | 30 +- opcodes/riscv-opc.c | 1456 +++++---- sim/ChangeLog | 7 + sim/configure | 16 +- sim/configure.ac | 16 +- sim/testsuite/ChangeLog | 41 + sim/testsuite/Makefile.in | 9 +- sim/testsuite/{sim => }/aarch64/ChangeLog | 0 sim/testsuite/{sim => }/aarch64/adds.s | 0 sim/testsuite/{sim => }/aarch64/addv.s | 0 sim/testsuite/{sim => }/aarch64/allinsn.exp | 0 sim/testsuite/{sim => }/aarch64/bit.s | 0 sim/testsuite/{sim => }/aarch64/cmtst.s | 0 sim/testsuite/{sim => }/aarch64/cnt.s | 0 sim/testsuite/{sim => }/aarch64/fcmXX.s | 0 sim/testsuite/{sim => }/aarch64/fcmp.s | 0 sim/testsuite/{sim => }/aarch64/fcsel.s | 0 sim/testsuite/{sim => }/aarch64/fcvtl.s | 0 sim/testsuite/{sim => }/aarch64/fcvtz.s | 0 sim/testsuite/{sim => }/aarch64/fminnm.s | 0 sim/testsuite/{sim => }/aarch64/fstur.s | 0 sim/testsuite/{sim => }/aarch64/ldn_multiple.s | 0 sim/testsuite/{sim => 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sim/testsuite/{sim => }/bfin/c_seq_ac_raise_mv.S | 0 .../{sim => }/bfin/c_seq_ac_raise_mv_ppop.S | 0 .../{sim => }/bfin/c_seq_ac_regmv_pushpop.S | 0 .../{sim => }/bfin/c_seq_dec_raise_pushpop.S | 0 .../{sim => }/bfin/c_seq_ex1_brcc_mv_pop.S | 0 .../{sim => }/bfin/c_seq_ex1_call_mv_pop.S | 0 sim/testsuite/{sim => }/bfin/c_seq_ex1_j_mv_pop.S | 0 .../{sim => }/bfin/c_seq_ex1_raise_brcc_mv_pop.S | 0 .../{sim => }/bfin/c_seq_ex1_raise_call_mv_pop.S | 0 .../{sim => }/bfin/c_seq_ex1_raise_j_mv_pop.S | 0 .../{sim => }/bfin/c_seq_ex2_brcc_mp_mv_pop.S | 0 sim/testsuite/{sim => }/bfin/c_seq_ex2_mmr_mvpop.S | 0 .../{sim => }/bfin/c_seq_ex2_mmrj_mvpop.S | 0 .../{sim => }/bfin/c_seq_ex2_raise_mmr_mvpop.S | 0 .../{sim => }/bfin/c_seq_ex2_raise_mmrj_mvpop.S | 0 .../{sim => }/bfin/c_seq_ex3_ls_brcc_mvp.S | 0 .../{sim => }/bfin/c_seq_ex3_ls_mmr_mvp.S | 0 .../{sim => }/bfin/c_seq_ex3_ls_mmrj_mvp.S | 0 .../{sim => }/bfin/c_seq_ex3_raise_ls_mmrj_mvp.S | 0 .../{sim => }/bfin/c_seq_wb_cs_lsmmrj_mvp.S | 0 .../{sim => }/bfin/c_seq_wb_raisecs_lsmmrj_mvp.S | 0 .../{sim => }/bfin/c_seq_wb_rti_lsmmrj_mvp.S | 0 .../{sim => }/bfin/c_seq_wb_rtn_lsmmrj_mvp.S | 0 .../{sim => }/bfin/c_seq_wb_rtx_lsmmrj_mvp.S | 0 sim/testsuite/{sim => }/bfin/c_ujump.s | 0 sim/testsuite/{sim => }/bfin/cc-alu.S | 0 sim/testsuite/{sim => }/bfin/cc-astat-bits.s | 0 sim/testsuite/{sim => }/bfin/cc0.s | 0 sim/testsuite/{sim => }/bfin/cc1.s | 0 sim/testsuite/{sim => }/bfin/cc5.S | 0 sim/testsuite/{sim => }/bfin/cec-exact-exception.S | 0 sim/testsuite/{sim => }/bfin/cec-ifetch.S | 0 sim/testsuite/{sim => }/bfin/cec-multi-pending.S | 0 sim/testsuite/{sim => }/bfin/cec-no-snen-reti.S | 0 .../{sim => }/bfin/cec-non-operating-env.s | 0 sim/testsuite/{sim => }/bfin/cec-raise-reti.S | 0 sim/testsuite/{sim => }/bfin/cec-snen-reti.S | 0 sim/testsuite/{sim => }/bfin/cec-syscfg-ssstep.S | 0 sim/testsuite/{sim => }/bfin/cec-system-call.S | 0 sim/testsuite/{sim => }/bfin/cir.s | 0 sim/testsuite/{sim => }/bfin/cir1.s | 0 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sim/testsuite/{sim => }/bfin/c_compi2opd_dr_add_i7_n.s (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opd_dr_add_i7_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opd_dr_eq_i7_n.s (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opd_dr_eq_i7_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opd_flags.S (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opd_flags_2.S (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opp_pr_add_i7_n.s (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opp_pr_add_i7_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opp_pr_eq_i7_n.s (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opp_pr_eq_i7_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_dagmodik_lnz_imgebl.s (100%) rename sim/testsuite/{sim => }/bfin/c_dagmodik_lnz_imltbl.s (100%) rename sim/testsuite/{sim => }/bfin/c_dagmodik_lz_inc_dec.s (100%) rename sim/testsuite/{sim => }/bfin/c_dagmodim_lnz_imgebl.s (100%) rename sim/testsuite/{sim => }/bfin/c_dagmodim_lnz_imltbl.s (100%) rename sim/testsuite/{sim => }/bfin/c_dagmodim_lz_inc_dec.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_a0_pm_a1.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_a0a1s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_a_abs_a.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_a_neg_a.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_aa_absabs.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_aa_negneg.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_abs.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_absabs.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_alhwx.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_awx.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_byteop1ew.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_byteop2.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_byteop3.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_bytepack.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_byteunpack.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_disalnexcpt.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_max.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_maxmax.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_min.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_minmin.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_mix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_r_lh_a0pa1.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_r_negneg.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_rnd12_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_rnd12_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_rnd20_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_rnd20_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_m.s (100%) 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(100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpmmp_sft.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpmmp_sft_x.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrppmm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrppmm_sft.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrppmm_sft_x.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_saa.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_sat_aa.S (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_search.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_sgn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_a1a0.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_a1a0_iuw32.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_a1a0_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_ih.s (100%) rename sim/testsuite/{sim => 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sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_mix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_ih.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_iu.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m.s (100%) rename sim/testsuite/{sim => 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sim/testsuite/{sim => }/bfin/c_dsp32shift_ahh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahh_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_align16.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_align24.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_align8.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_amix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_bitmux.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_bxor.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expadj_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expadj_l.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expadj_r.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expexp_r.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_fdepx.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_fextx.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lf.s (100%) rename sim/testsuite/{sim => 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}/bfin/c_dsp32shiftim_a0alr.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_af.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_af_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_ln.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_ln_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_lp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_lp_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_rn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_rn_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_rp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_rp_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahh_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_amix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lf.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_ln.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_lp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_rn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_rp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lmix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_rot.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_ippm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drhi_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drhi_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drlo_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drlo_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_i.s (100%) rename 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sim/testsuite/{sim => }/bfin/c_progctrl_excpt.S (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_jump_pcpr.s (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_jump_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_nop.s (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_raise_rt_i_n.S (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_rts.s (100%) rename sim/testsuite/{sim => }/bfin/c_ptr2op_pr_neg_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ptr2op_pr_sft_2_1.s (100%) rename sim/testsuite/{sim => }/bfin/c_ptr2op_pr_shadd_1_2.s (100%) rename sim/testsuite/{sim => }/bfin/c_pushpopmultiple_dp.s (100%) rename sim/testsuite/{sim => }/bfin/c_pushpopmultiple_dp_pair.s (100%) rename sim/testsuite/{sim => }/bfin/c_pushpopmultiple_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_pushpopmultiple_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_acc_acc.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_dag_lz_dep.s (100%) rename sim/testsuite/{sim => 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}/bfin/c_seq_ex3_ls_brcc_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex3_ls_mmr_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex3_ls_mmrj_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex3_raise_ls_mmrj_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_wb_cs_lsmmrj_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_wb_raisecs_lsmmrj_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_wb_rti_lsmmrj_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_wb_rtn_lsmmrj_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_wb_rtx_lsmmrj_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_ujump.s (100%) rename sim/testsuite/{sim => }/bfin/cc-alu.S (100%) rename sim/testsuite/{sim => }/bfin/cc-astat-bits.s (100%) rename sim/testsuite/{sim => }/bfin/cc0.s (100%) rename sim/testsuite/{sim => }/bfin/cc1.s (100%) rename sim/testsuite/{sim => }/bfin/cc5.S (100%) rename sim/testsuite/{sim => }/bfin/cec-exact-exception.S (100%) rename sim/testsuite/{sim => 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=> }/bfin/dsp_d0.s (100%) rename sim/testsuite/{sim => }/bfin/dsp_d1.s (100%) rename sim/testsuite/{sim => }/bfin/dsp_neg.S (100%) rename sim/testsuite/{sim => }/bfin/dsp_s1.s (100%) rename sim/testsuite/{sim => }/bfin/e0.s (100%) rename sim/testsuite/{sim => }/bfin/edn_snafu.s (100%) rename sim/testsuite/{sim => }/bfin/eu_dsp32mac_s.s (100%) rename sim/testsuite/{sim => }/bfin/events.s (100%) rename sim/testsuite/{sim => }/bfin/f221.s (100%) rename sim/testsuite/{sim => }/bfin/fact.s (100%) rename sim/testsuite/{sim => }/bfin/fir.s (100%) rename sim/testsuite/{sim => }/bfin/fsm.s (100%) rename sim/testsuite/{sim => }/bfin/greg2.s (100%) rename sim/testsuite/{sim => }/bfin/hwloop-bits.S (100%) rename sim/testsuite/{sim => }/bfin/hwloop-branch-in.s (100%) rename sim/testsuite/{sim => }/bfin/hwloop-branch-out.s (100%) rename sim/testsuite/{sim => }/bfin/hwloop-lt-bits.s (100%) rename sim/testsuite/{sim => }/bfin/hwloop-nested.s (100%) rename sim/testsuite/{sim => }/bfin/i0.s (100%) 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rename sim/testsuite/{sim => }/frv/fr550/maddaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/maddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/maddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/masaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mdaddaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mdasaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mdsubaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mmrdhs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mmrdhu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqaddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqaddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqmacxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqsubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqsubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqxmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqxmacxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/msubaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/msubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/msubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mtrap.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/udiv.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/udivi.cgs (100%) rename sim/testsuite/{sim => }/frv/fsqrtd.cgs (100%) rename sim/testsuite/{sim => }/frv/fsqrts.cgs (100%) rename sim/testsuite/{sim => }/frv/fstoi.cgs (100%) rename sim/testsuite/{sim => }/frv/fsubd.cgs (100%) rename sim/testsuite/{sim => }/frv/fsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/fteq.cgs (100%) rename sim/testsuite/{sim => }/frv/ftge.cgs (100%) rename sim/testsuite/{sim => }/frv/ftgt.cgs (100%) rename sim/testsuite/{sim => }/frv/ftieq.cgs (100%) rename sim/testsuite/{sim => }/frv/ftige.cgs (100%) rename sim/testsuite/{sim => }/frv/ftigt.cgs (100%) rename sim/testsuite/{sim => }/frv/ftile.cgs (100%) rename sim/testsuite/{sim => }/frv/ftilg.cgs (100%) rename sim/testsuite/{sim => }/frv/ftilt.cgs (100%) rename sim/testsuite/{sim => }/frv/ftine.cgs (100%) rename sim/testsuite/{sim => }/frv/ftino.cgs (100%) rename sim/testsuite/{sim => }/frv/ftio.cgs (100%) rename sim/testsuite/{sim => }/frv/ftira.cgs (100%) rename sim/testsuite/{sim => }/frv/ftiu.cgs (100%) rename sim/testsuite/{sim => }/frv/ftiue.cgs (100%) rename sim/testsuite/{sim => }/frv/ftiug.cgs (100%) rename sim/testsuite/{sim => }/frv/ftiuge.cgs (100%) rename sim/testsuite/{sim => }/frv/ftiul.cgs (100%) rename sim/testsuite/{sim => }/frv/ftle.cgs (100%) rename sim/testsuite/{sim => }/frv/ftlg.cgs (100%) rename sim/testsuite/{sim => }/frv/ftlt.cgs (100%) rename sim/testsuite/{sim => }/frv/ftne.cgs (100%) rename sim/testsuite/{sim => }/frv/ftno.cgs (100%) rename sim/testsuite/{sim => }/frv/fto.cgs (100%) rename sim/testsuite/{sim => }/frv/ftra.cgs (100%) rename sim/testsuite/{sim => }/frv/ftu.cgs (100%) rename sim/testsuite/{sim => }/frv/ftue.cgs (100%) rename sim/testsuite/{sim => }/frv/ftug.cgs (100%) rename sim/testsuite/{sim => }/frv/ftuge.cgs (100%) rename sim/testsuite/{sim => }/frv/ftul.cgs (100%) rename sim/testsuite/{sim => }/frv/ftule.cgs (100%) create mode 100644 sim/testsuite/frv/grloop.ms create mode 100644 sim/testsuite/frv/hello.ms rename sim/testsuite/{sim => }/frv/icei.cgs (100%) rename sim/testsuite/{sim => }/frv/ici.cgs (100%) rename sim/testsuite/{sim => }/frv/icpl.cgs (100%) rename sim/testsuite/{sim => }/frv/icul.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts.exp (100%) rename sim/testsuite/{sim => }/frv/interrupts/Ipipe-fr400.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/Ipipe-fr500.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/badalign-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/badalign.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/compound-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/compound.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/data_store_error-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/data_store_error.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/fp_exception-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/fp_exception.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/illinsn.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/insn_access_error-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/insn_access_error.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/mp_exception.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/privileged_instruction.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/regalign.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/reset.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/shadow_regs.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/timer.cgs (100%) rename sim/testsuite/{sim => }/frv/jmpil.cgs (100%) rename sim/testsuite/{sim => }/frv/jmpl.cgs (100%) rename sim/testsuite/{sim => }/frv/jmpl.pcgs (100%) rename sim/testsuite/{sim => }/frv/ld.cgs (100%) rename sim/testsuite/{sim => }/frv/ldbf.cgs (100%) rename sim/testsuite/{sim => }/frv/ldbfi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldbfu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldc.cgs (100%) rename sim/testsuite/{sim => }/frv/ldcu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldd.cgs (100%) rename sim/testsuite/{sim => }/frv/lddc.cgs (100%) rename sim/testsuite/{sim => }/frv/lddcu.cgs (100%) rename sim/testsuite/{sim => }/frv/lddf.cgs (100%) rename sim/testsuite/{sim => }/frv/lddfi.cgs (100%) rename sim/testsuite/{sim => }/frv/lddfu.cgs (100%) rename sim/testsuite/{sim => }/frv/lddi.cgs (100%) rename sim/testsuite/{sim => }/frv/lddu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldf.cgs (100%) rename sim/testsuite/{sim => }/frv/ldfi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldfu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldhf.cgs (100%) rename sim/testsuite/{sim => }/frv/ldhfi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldhfu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldq.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqc.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqcu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqf.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqfi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqfu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldsb.cgs (100%) rename sim/testsuite/{sim => }/frv/ldsbi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldsbu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldsh.cgs (100%) rename sim/testsuite/{sim => }/frv/ldshi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldshu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldub.cgs (100%) rename sim/testsuite/{sim => }/frv/ldubi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldubu.cgs (100%) rename sim/testsuite/{sim => }/frv/lduh.cgs (100%) rename sim/testsuite/{sim => }/frv/lduhi.cgs (100%) rename sim/testsuite/{sim => }/frv/lduhu.cgs (100%) rename sim/testsuite/{sim => }/frv/lrbranch.pcgs (100%) rename sim/testsuite/{sim => }/frv/mabshs.cgs (100%) rename sim/testsuite/{sim => }/frv/maddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/maddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/mand.cgs (100%) rename sim/testsuite/{sim => }/frv/maveh.cgs (100%) rename sim/testsuite/{sim => }/frv/mbtoh.cgs (100%) rename sim/testsuite/{sim => }/frv/mbtohe.cgs (100%) rename sim/testsuite/{sim => }/frv/mclracc.cgs (100%) rename sim/testsuite/{sim => }/frv/mcmpsh.cgs (100%) rename sim/testsuite/{sim => }/frv/mcmpuh.cgs (100%) rename sim/testsuite/{sim => }/frv/mcop1.cgs (100%) rename sim/testsuite/{sim => }/frv/mcop2.cgs (100%) rename sim/testsuite/{sim => }/frv/mcplhi.cgs (100%) rename sim/testsuite/{sim => }/frv/mcpli.cgs (100%) rename sim/testsuite/{sim => }/frv/mcpxis.cgs (100%) rename sim/testsuite/{sim => }/frv/mcpxiu.cgs (100%) rename sim/testsuite/{sim => }/frv/mcpxrs.cgs (100%) rename sim/testsuite/{sim => }/frv/mcpxru.cgs (100%) rename sim/testsuite/{sim => }/frv/mcut.cgs (100%) rename sim/testsuite/{sim => }/frv/mcuti.cgs (100%) rename sim/testsuite/{sim => }/frv/mcutss.cgs (100%) rename sim/testsuite/{sim => }/frv/mcutssi.cgs (100%) rename sim/testsuite/{sim => }/frv/mdaddaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/mdasaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/mdcutssi.cgs (100%) rename sim/testsuite/{sim => }/frv/mdpackh.cgs (100%) rename sim/testsuite/{sim => }/frv/mdrotli.cgs (100%) rename sim/testsuite/{sim => }/frv/mdsubaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/mdunpackh.cgs (100%) rename sim/testsuite/{sim => }/frv/membar.cgs (100%) rename sim/testsuite/{sim => }/frv/mexpdhd.cgs (100%) rename sim/testsuite/{sim => }/frv/mexpdhw.cgs (100%) rename sim/testsuite/{sim => }/frv/mhdseth.cgs (100%) rename sim/testsuite/{sim => }/frv/mhdsets.cgs (100%) rename sim/testsuite/{sim => }/frv/mhsethih.cgs (100%) rename sim/testsuite/{sim => }/frv/mhsethis.cgs (100%) rename sim/testsuite/{sim => }/frv/mhsetloh.cgs (100%) rename sim/testsuite/{sim => }/frv/mhsetlos.cgs (100%) rename sim/testsuite/{sim => }/frv/mhtob.cgs (100%) create mode 100644 sim/testsuite/frv/misc.exp rename sim/testsuite/{sim => }/frv/mmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/mmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/mmrdhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mmrdhu.cgs (100%) rename sim/testsuite/{sim => }/frv/mmulhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mmulhu.cgs (100%) rename sim/testsuite/{sim => }/frv/mmulxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mmulxhu.cgs (100%) rename sim/testsuite/{sim => }/frv/mnop.cgs (100%) rename sim/testsuite/{sim => }/frv/mnot.cgs (100%) rename sim/testsuite/{sim => }/frv/mor.cgs (100%) rename sim/testsuite/{sim => }/frv/mov.cgs (100%) rename sim/testsuite/{sim => }/frv/movfg.cgs (100%) rename sim/testsuite/{sim => }/frv/movfgd.cgs (100%) rename sim/testsuite/{sim => }/frv/movfgq.cgs (100%) rename sim/testsuite/{sim => }/frv/movgf.cgs (100%) rename sim/testsuite/{sim => }/frv/movgfd.cgs (100%) rename sim/testsuite/{sim => }/frv/movgfq.cgs (100%) rename sim/testsuite/{sim => }/frv/movgs.cgs (100%) rename sim/testsuite/{sim => }/frv/movsg.cgs (100%) rename sim/testsuite/{sim => }/frv/mpackh.cgs (100%) rename sim/testsuite/{sim => }/frv/mqcpxis.cgs (100%) rename sim/testsuite/{sim => }/frv/mqcpxiu.cgs (100%) rename sim/testsuite/{sim => }/frv/mqcpxrs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqcpxru.cgs (100%) rename sim/testsuite/{sim => }/frv/mqlclrhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqlmths.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmacxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmulhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmulhu.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmulxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmulxhu.cgs (100%) rename sim/testsuite/{sim => }/frv/mqsaths.cgs (100%) rename sim/testsuite/{sim => }/frv/mqsllhi.cgs (100%) rename sim/testsuite/{sim => }/frv/mqsrahi.cgs (100%) rename sim/testsuite/{sim => }/frv/mqxmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqxmacxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mrdacc.cgs (100%) rename sim/testsuite/{sim => }/frv/mrdaccg.cgs (100%) rename sim/testsuite/{sim => }/frv/mrotli.cgs (100%) rename sim/testsuite/{sim => }/frv/mrotri.cgs (100%) rename sim/testsuite/{sim => }/frv/msaths.cgs (100%) rename sim/testsuite/{sim => }/frv/msathu.cgs (100%) rename sim/testsuite/{sim => }/frv/msllhi.cgs (100%) rename sim/testsuite/{sim => }/frv/msrahi.cgs (100%) rename sim/testsuite/{sim => }/frv/msrlhi.cgs (100%) rename sim/testsuite/{sim => }/frv/msubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/msubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/mtrap.cgs (100%) rename sim/testsuite/{sim => }/frv/munpackh.cgs (100%) rename sim/testsuite/{sim => }/frv/mwcut.cgs (100%) rename sim/testsuite/{sim => }/frv/mwcuti.cgs (100%) rename sim/testsuite/{sim => }/frv/mwtacc.cgs (100%) rename sim/testsuite/{sim => }/frv/mwtaccg.cgs (100%) rename sim/testsuite/{sim => }/frv/mxor.cgs (100%) rename sim/testsuite/{sim => }/frv/nandcr.cgs (100%) rename sim/testsuite/{sim => }/frv/nandncr.cgs (100%) rename sim/testsuite/{sim => }/frv/nfadds.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdadds.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdcmps.cgs (100%) rename sim/testsuite/{sim => }/frv/nfddivs.cgs (100%) rename sim/testsuite/{sim => }/frv/nfditos.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdivs.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdmadds.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdmas.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdmss.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdmulcs.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdmuls.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdsads.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdsqrts.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdstoi.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/nfitos.cgs (100%) rename sim/testsuite/{sim => }/frv/nfmadds.cgs (100%) rename sim/testsuite/{sim => }/frv/nfmas.cgs (100%) rename sim/testsuite/{sim => }/frv/nfmss.cgs (100%) rename sim/testsuite/{sim => }/frv/nfmsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/nfmuls.cgs (100%) rename sim/testsuite/{sim => }/frv/nfsqrts.cgs (100%) rename sim/testsuite/{sim => }/frv/nfstoi.cgs (100%) rename sim/testsuite/{sim => }/frv/nfsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/nld.cgs (100%) rename sim/testsuite/{sim => }/frv/nldbf.cgs (100%) rename sim/testsuite/{sim => }/frv/nldbfi.cgs (100%) rename sim/testsuite/{sim => }/frv/nldbfu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldd.cgs (100%) rename sim/testsuite/{sim => }/frv/nlddf.cgs (100%) rename sim/testsuite/{sim => }/frv/nlddfi.cgs (100%) rename sim/testsuite/{sim => }/frv/nlddfu.cgs (100%) rename sim/testsuite/{sim => }/frv/nlddi.cgs (100%) rename sim/testsuite/{sim => }/frv/nlddu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldf.cgs (100%) rename sim/testsuite/{sim => }/frv/nldfi.cgs (100%) rename sim/testsuite/{sim => }/frv/nldfu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldhf.cgs (100%) rename sim/testsuite/{sim => }/frv/nldhfi.cgs (100%) rename sim/testsuite/{sim => }/frv/nldhfu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldi.cgs (100%) rename sim/testsuite/{sim => }/frv/nldq.cgs (100%) rename sim/testsuite/{sim => }/frv/nldqf.cgs (100%) rename sim/testsuite/{sim => }/frv/nldqfi.cgs (100%) rename sim/testsuite/{sim => }/frv/nldqfu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldqu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldsb.cgs (100%) rename sim/testsuite/{sim => }/frv/nldsbi.cgs (100%) rename sim/testsuite/{sim => }/frv/nldsbu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldsh.cgs (100%) rename sim/testsuite/{sim => }/frv/nldshi.cgs (100%) rename sim/testsuite/{sim => }/frv/nldshu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldub.cgs (100%) rename sim/testsuite/{sim => }/frv/nldubi.cgs (100%) rename sim/testsuite/{sim => }/frv/nldubu.cgs (100%) rename sim/testsuite/{sim => }/frv/nlduh.cgs (100%) rename sim/testsuite/{sim => }/frv/nlduhi.cgs (100%) rename sim/testsuite/{sim => }/frv/nlduhu.cgs (100%) rename sim/testsuite/{sim => }/frv/nop.cgs (100%) rename sim/testsuite/{sim => }/frv/norcr.cgs (100%) rename sim/testsuite/{sim => }/frv/norncr.cgs (100%) rename sim/testsuite/{sim => }/frv/not.cgs (100%) rename sim/testsuite/{sim => }/frv/notcr.cgs (100%) rename sim/testsuite/{sim => }/frv/nsdiv.cgs (100%) rename sim/testsuite/{sim => }/frv/nsdivi.cgs (100%) rename sim/testsuite/{sim => }/frv/nudiv.cgs (100%) rename sim/testsuite/{sim => }/frv/nudivi.cgs (100%) rename sim/testsuite/{sim => }/frv/or.cgs (100%) rename sim/testsuite/{sim => }/frv/orcc.cgs (100%) rename sim/testsuite/{sim => }/frv/orcr.cgs (100%) rename sim/testsuite/{sim => }/frv/ori.cgs (100%) rename sim/testsuite/{sim => }/frv/oricc.cgs (100%) rename sim/testsuite/{sim => }/frv/orncr.cgs (100%) rename sim/testsuite/{sim => }/frv/parallel.exp (100%) rename sim/testsuite/{sim => }/frv/ret.cgs (100%) rename sim/testsuite/{sim => }/frv/rett.cgs (100%) rename sim/testsuite/{sim => }/frv/scan.cgs (100%) rename sim/testsuite/{sim => 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