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from ccd4f446eb6 [LoopVectorizer] Fix for cost values of memory accesses. new 78f5683a63c [SchedModel] Fix for read advance cycles with implicit pse [...]
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Summary of changes: lib/CodeGen/ScheduleDAGInstrs.cpp | 20 +- test/CodeGen/AMDGPU/call-argument-types.ll | 22 +- test/CodeGen/AMDGPU/call-preserved-registers.ll | 36 +-- test/CodeGen/AMDGPU/callee-special-input-sgprs.ll | 3 +- test/CodeGen/AMDGPU/indirect-addressing-si.ll | 6 +- test/CodeGen/AMDGPU/inline-asm.ll | 4 +- test/CodeGen/AMDGPU/insert_vector_elt.ll | 2 +- test/CodeGen/AMDGPU/misched-killflags.mir | 12 +- test/CodeGen/AMDGPU/nested-calls.ll | 4 +- test/CodeGen/AMDGPU/undefined-subreg-liverange.ll | 12 +- test/CodeGen/ARM/Windows/chkstk-movw-movt-isel.ll | 6 +- test/CodeGen/ARM/Windows/chkstk.ll | 6 +- test/CodeGen/ARM/Windows/memset.ll | 4 +- test/CodeGen/ARM/arm-and-tst-peephole.ll | 2 +- test/CodeGen/ARM/arm-shrink-wrapping.ll | 28 +-- test/CodeGen/ARM/cortex-a57-misched-ldm-wrback.ll | 4 +- test/CodeGen/ARM/cortex-a57-misched-ldm.ll | 2 +- test/CodeGen/ARM/cortex-a57-misched-vldm-wrback.ll | 4 +- test/CodeGen/ARM/cortex-a57-misched-vldm.ll | 4 +- test/CodeGen/ARM/fp16-instructions.ll | 4 +- test/CodeGen/ARM/select.ll | 2 +- test/CodeGen/ARM/twoaddrinstr.ll | 4 +- test/CodeGen/ARM/vcombine.ll | 8 +- test/CodeGen/ARM/vuzp.ll | 242 ++++++++++----------- test/CodeGen/SystemZ/misched-readadvances.mir | 31 +++ .../Thumb2/umulo-128-legalisation-lowering.ll | 4 +- .../Thumb2/umulo-64-legalisation-lowering.ll | 4 +- test/CodeGen/X86/lsr-loop-exit-cond.ll | 8 +- test/CodeGen/X86/memset.ll | 2 +- test/CodeGen/X86/phys-reg-local-regalloc.ll | 4 +- test/CodeGen/X86/schedule-x86-64-shld.ll | 8 +- test/CodeGen/X86/schedule-x86_32.ll | 10 +- 32 files changed, 278 insertions(+), 234 deletions(-) create mode 100644 test/CodeGen/SystemZ/misched-readadvances.mir