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from 51856718a82 reassoc: Fix up another ICE with returns_twice call [PR109410] new 31eb8f18bbe RISC-V: Fix supporting data type according to RVV ISA. [PR109479]
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Summary of changes: gcc/config/riscv/riscv-vector-builtins-types.def | 348 ++++++++++----------- gcc/config/riscv/riscv-vector-builtins.cc | 14 +- gcc/config/riscv/riscv-vector-builtins.h | 3 +- gcc/config/riscv/riscv-vector-switch.def | 56 ++-- gcc/config/riscv/vector-iterators.md | 68 ++-- .../gcc.target/riscv/rvv/base/pr109479-1.c | 13 + .../gcc.target/riscv/rvv/base/pr109479-2.c | 13 + .../gcc.target/riscv/rvv/base/pr109479-3.c | 20 ++ .../gcc.target/riscv/rvv/base/pr109479-4.c | 20 ++ .../gcc.target/riscv/rvv/base/pr109479-5.c | 20 ++ .../gcc.target/riscv/rvv/base/pr109479-6.c | 20 ++ 11 files changed, 349 insertions(+), 246 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr109479-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr109479-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr109479-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr109479-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr109479-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr109479-6.c