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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allyesconfig in repository toolchain/ci/llvm-project.
from f42990e6874 [Mem2Reg] Don't call LBI.deleteValue on AllocInst/DbgVariab [...] adds e57c53df4fc [Mem2Reg] Simplify and micro optimize adds de20429cfc0 [Mem2Reg] Delete unused PointerAllocaValues adds d652bdd05f1 [c++20] Parsing support for module-declarations, import-dec [...] adds dc7000b384f [ConstantRange] Simplify unittests after getSetSize was removed adds b1b580e047a [c++20] Enable driver and frontend support for building and [...] adds 065480daf2e [clang-tidy] Add MagnitudeBitsUpperLimit option to bugpron [...] adds 12886f04eae Prevent unnecessary conversion from StringRef to C-string [NFC] adds b17e5ec61b5 [X86] Don't form masked vpcmp/vcmp/vptestm operations if th [...] adds 3c57976447b [X86] Move VPTESTM matching from the isel table to custom c [...] adds 72b976e5d72 [X86] Change IMUL with immediate instruction order to ri8 i [...] adds 96950f1fa98 [X86] Put the locked mi8 instrutions above the locked mi/mi [...] adds 5b92eb007b8 [X86] Redefine KUNPCK instructions to take a narrower sourc [...] adds 63fe2593ae5 llvm-undname: Fix another crash-on-invalid found by oss-fuzz adds ce1452ad27e gn build: Merge r358272 adds 6de31be67e7 gn build: Merge r358243 adds 274f305a418 gn build: Merge r358297 adds ae050d214b9 llvm-undname: Fix oss-fuzz-foudn crash-on-invalid with inco [...] adds d189680baa0 [GlobalISel] Introduce a CSEConfigBase class to allow targe [...] adds 946b1246d6c [GlobalISel] Enable CSE in the IRTranslator & legalizer for [...] adds 489f8255fcb [Sparc] Fix typo. NFC. adds abd87ff48b9 [X86] Regenerate checks for domain-reassignment.mir
No new revisions were added by this update.
Summary of changes: .../bugprone/TooSmallLoopVariableCheck.cpp | 50 +- .../bugprone/TooSmallLoopVariableCheck.h | 8 +- clang-tools-extra/docs/ReleaseNotes.rst | 6 + .../checks/bugprone-too-small-loop-variable.rst | 17 + ...all-loop-variable-magniute-bits-upper-limit.cpp | 23 + .../bugprone-too-small-loop-variable.cpp | 6 +- .../include/clang/Basic/DiagnosticFrontendKinds.td | 7 +- clang/include/clang/Basic/DiagnosticParseKinds.td | 11 +- clang/include/clang/Basic/DiagnosticSemaKinds.td | 12 +- clang/include/clang/Lex/Preprocessor.h | 1 + clang/include/clang/Parse/Parser.h | 10 +- clang/include/clang/Sema/Sema.h | 35 +- clang/lib/Driver/ToolChains/Clang.cpp | 15 +- clang/lib/Frontend/FrontendActions.cpp | 6 +- clang/lib/Lex/PPDirectives.cpp | 4 + clang/lib/Lex/Preprocessor.cpp | 1 + clang/lib/Parse/Parser.cpp | 204 ++++++- clang/lib/Sema/Sema.cpp | 32 +- clang/lib/Sema/SemaDecl.cpp | 121 +++- clang/test/CXX/basic/basic.link/p1.cpp | 37 ++ clang/test/CXX/basic/basic.link/p3.cpp | 53 ++ clang/test/CXX/module/module.unit/p3.cpp | 4 + clang/test/CXX/module/module.unit/p8.cpp | 40 ++ .../basic/basic.link/module-declaration.cpp | 34 +- clang/test/Driver/modules.cpp | 74 +++ lldb/source/Utility/ConstString.cpp | 2 +- llvm/include/llvm/CodeGen/CSEConfigBase.h | 28 + llvm/include/llvm/CodeGen/GlobalISel/CSEInfo.h | 34 +- llvm/include/llvm/CodeGen/TargetPassConfig.h | 4 + llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp | 20 +- llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 21 +- llvm/lib/CodeGen/GlobalISel/Legalizer.cpp | 4 +- llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp | 6 +- llvm/lib/CodeGen/TargetPassConfig.cpp | 7 +- llvm/lib/Demangle/MicrosoftDemangle.cpp | 9 +- llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp | 5 +- llvm/lib/Target/AArch64/AArch64TargetMachine.cpp | 7 + llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 28 +- llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 6 + llvm/lib/Target/ARM/ARMTargetMachine.cpp | 6 + llvm/lib/Target/Mips/MipsTargetMachine.cpp | 6 + llvm/lib/Target/Sparc/SparcRegisterInfo.cpp | 4 +- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 361 ++++++++++++ llvm/lib/Target/X86/X86InstrAVX512.td | 522 +++++++---------- llvm/lib/Target/X86/X86InstrArithmetic.td | 65 ++- llvm/lib/Target/X86/X86InstrCompiler.td | 50 +- llvm/lib/Target/X86/X86TargetMachine.cpp | 6 + .../Transforms/Utils/PromoteMemoryToRegister.cpp | 27 +- .../AArch64/GlobalISel/arm64-irtranslator.ll | 29 +- .../AArch64/GlobalISel/call-translator-ios.ll | 2 +- .../CodeGen/AArch64/GlobalISel/call-translator.ll | 2 +- .../CodeGen/AArch64/GlobalISel/legalize-cmp.mir | 3 +- .../CodeGen/AArch64/GlobalISel/legalize-div.mir | 8 +- .../CodeGen/AArch64/GlobalISel/legalize-ext.mir | 5 +- .../legalize-load-store-s128-unaligned.mir | 3 +- .../AArch64/GlobalISel/legalize-merge-values.mir | 3 +- .../CodeGen/AArch64/GlobalISel/legalize-phi.mir | 3 +- .../CodeGen/AArch64/GlobalISel/legalize-rem.mir | 5 +- .../CodeGen/AArch64/GlobalISel/legalize-shift.mir | 15 +- .../CodeGen/AArch64/GlobalISel/legalize-vaarg.mir | 10 +- .../CodeGen/AArch64/GlobalISel/translate-gep.ll | 21 +- .../AMDGPU/GlobalISel/legalize-addrspacecast.mir | 34 +- .../CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir | 240 ++++---- .../CodeGen/AMDGPU/GlobalISel/legalize-bswap.mir | 6 +- .../AMDGPU/GlobalISel/legalize-ctlz-zero-undef.mir | 9 +- .../CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir | 9 +- .../CodeGen/AMDGPU/GlobalISel/legalize-ctpop.mir | 6 +- .../AMDGPU/GlobalISel/legalize-cttz-zero-undef.mir | 6 +- .../CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir | 9 +- .../CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir | 6 +- .../CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir | 240 +++----- .../AMDGPU/GlobalISel/legalize-merge-values.mir | 37 +- .../CodeGen/AMDGPU/GlobalISel/legalize-shl.mir | 300 ++++------ .../CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir | 18 +- .../AMDGPU/GlobalISel/legalize-unmerge-values.mir | 133 ++--- .../CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir | 18 +- .../ARM/GlobalISel/arm-legalize-bitcounts.mir | 2 - .../CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir | 8 - .../CodeGen/ARM/GlobalISel/arm-legalize-fp.mir | 16 +- .../ARM/GlobalISel/arm-legalize-load-store.mir | 12 +- .../test/CodeGen/Mips/GlobalISel/legalizer/add.mir | 12 +- .../test/CodeGen/Mips/GlobalISel/legalizer/mul.mir | 30 +- .../Mips/GlobalISel/legalizer/rem_and_div.mir | 92 ++- .../test/CodeGen/Mips/GlobalISel/legalizer/sub.mir | 12 +- llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll | 16 +- llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll | 40 +- .../CodeGen/Mips/GlobalISel/llvm-ir/rem_and_div.ll | 36 +- llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sub.ll | 20 +- llvm/test/CodeGen/X86/GlobalISel/add-ext.ll | 79 +-- llvm/test/CodeGen/X86/GlobalISel/gep.ll | 16 +- .../X86/GlobalISel/irtranslator-callingconv.ll | 38 +- .../X86/GlobalISel/legalize-memop-scalar-32.mir | 3 +- .../x86_64-irtranslator-struct-return.ll | 39 +- llvm/test/CodeGen/X86/avx512-vec-cmp.ll | 4 +- .../CodeGen/X86/avx512vl-intrinsics-upgrade.ll | 60 +- llvm/test/CodeGen/X86/domain-reassignment.mir | 7 +- llvm/test/CodeGen/X86/kshift.ll | 116 ++-- llvm/test/CodeGen/X86/movmsk-cmp.ll | 36 +- llvm/test/CodeGen/X86/prefer-avx256-mask-extend.ll | 72 +-- .../test/CodeGen/X86/prefer-avx256-mask-shuffle.ll | 28 +- llvm/test/CodeGen/X86/setcc-lowering.ll | 3 +- llvm/test/CodeGen/X86/vec_uaddo.ll | 13 +- llvm/test/CodeGen/X86/vector-compare-all_of.ll | 6 +- llvm/test/CodeGen/X86/vector-fshl-128.ll | 494 ++++++++-------- llvm/test/CodeGen/X86/vector-fshl-256.ll | 488 ++++++++-------- llvm/test/CodeGen/X86/vector-fshl-512.ll | 632 ++++++++++----------- llvm/test/CodeGen/X86/vector-fshr-128.ll | 494 ++++++++-------- llvm/test/CodeGen/X86/vector-fshr-256.ll | 488 ++++++++-------- llvm/test/CodeGen/X86/vector-fshr-512.ll | 560 +++++++++--------- llvm/test/CodeGen/X86/vector-lzcnt-512.ll | 76 ++- llvm/test/Demangle/invalid-manglings.test | 15 + llvm/unittests/CodeGen/GlobalISel/CSETest.cpp | 2 +- llvm/unittests/IR/ConstantRangeTest.cpp | 37 +- .../clang-tools-extra/unittests/clangd/BUILD.gn | 1 + llvm/utils/gn/secondary/clang/lib/CodeGen/BUILD.gn | 1 + .../gn/secondary/llvm/unittests/Support/BUILD.gn | 1 + 116 files changed, 3847 insertions(+), 3477 deletions(-) create mode 100644 clang-tools-extra/test/clang-tidy/bugprone-too-small-loop-varia [...] create mode 100644 clang/test/CXX/basic/basic.link/p1.cpp create mode 100644 clang/test/CXX/basic/basic.link/p3.cpp create mode 100644 clang/test/CXX/module/module.unit/p3.cpp create mode 100644 clang/test/CXX/module/module.unit/p8.cpp create mode 100644 clang/test/Driver/modules.cpp create mode 100644 llvm/include/llvm/CodeGen/CSEConfigBase.h