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from 9b4235c03c5 [DAGCombine] Improve ReduceLoadWidth for SRL new 107f6100d79 [AArch64] Add patterns matching (fabs (fsub x y)) to (fabd x y)
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Summary of changes: lib/Target/AArch64/AArch64InstrInfo.td | 13 ++++++ test/CodeGen/AArch64/arm64-vabs.ll | 53 +++++++++++++++++++++++ test/CodeGen/AArch64/fp16_intrinsic_scalar_2op.ll | 11 +++++ test/CodeGen/AArch64/fp16_intrinsic_vector_2op.ll | 42 ++++++++++++++++++ 4 files changed, 119 insertions(+)