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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-lts-defconfig in repository toolchain/ci/qemu.
from 1c81a38c5a Merge remote-tracking branch 'remotes/legoater/tags/pull-asp [...] adds e59a7e0ec5 elf2dmp: Check curl_easy_setopt() return value adds f015cbb546 elf2dmp: Fail cleanly if PDB file specifies zero block_size adds b62ceeaf80 target/arm: Don't skip M-profile reset entirely in user mode adds 4a888072c8 target/arm: Always clear exclusive monitor on reset adds 1426f2449e target/arm: Consolidate ifdef blocks in reset adds 9cee1efe92 hw/intc: Set GIC maintenance interrupt level to only 0 or 1 adds 0130895ddf arm: Move PMC register definitions to internals.h adds 5b3e751724 hvf: Add execute to dirty log permission bitmap adds ce7f5b1c50 hvf: Introduce hvf_arch_init() callback adds a1477da3dd hvf: Add Apple Silicon support adds 219c101fa7 arm/hvf: Add a WFI handler adds 585df85efe hvf: arm: Implement -cpu host adds 2c9c0bf9d1 hvf: arm: Implement PSCI handling adds 844a06bbe4 arm: Add Hypervisor.framework build target adds dd43ac07ef hvf: arm: Add rudimentary PMC support adds 84848481c3 target/arm: Avoid goto_tb if we're trying to exit to the main loop adds 85e7d1e9ff target/arm: Enforce that FPDSCR.LTPSIZE is 4 on inbound migration adds 2670221397 target/arm: Add TB flag for "MVE insns not predicated" adds 451f9d66cf target/arm: Optimize MVE logic ops adds bc3087f253 target/arm: Optimize MVE arithmetic ops adds 4b1561c472 target/arm: Optimize MVE VNEG, VABS adds f8d94803f1 target/arm: Optimize MVE VDUP adds 5cf525a8a6 target/arm: Optimize MVE VMVN adds 752970ef7c target/arm: Optimize MVE VSHL, VSHR immediate forms adds a7789fabe1 target/arm: Optimize MVE VSHLL and VMOVL adds ce75c43f6d target/arm: Optimize MVE VSLI and VSRI adds 4b445c926a target/arm: Optimize MVE 1op-immediate insns adds 81ceb36b96 Merge remote-tracking branch 'remotes/pmaydell/tags/pull-tar [...] adds a44da25aa6 target/riscv: Update the ePMP CSR address adds 15732b8ed2 target/riscv: Fix satp write adds 0f0b70eeec target/riscv: Expose interrupt pending bits as GPIO lines adds a714b8aa02 hw/intc: sifive_clint: Use RISC-V CPU GPIO lines adds e5cc6aaeb5 hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO lines adds f436ecc315 hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines adds 57a3a62265 hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines adds 5bf6f1acdd hw/timer: Add SiFive PWM support adds ea6eaa0604 sifive_u: Connect the SiFive PWM device adds cc63a18282 hw/intc: Rename sifive_clint sources to riscv_aclint sources adds b8fb878aa2 hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT adds 0ffc1a9522 hw/riscv: virt: Re-factor FDT generation adds 954886ea6d hw/riscv: virt: Add optional ACLINT support to virt machine adds de7c7988d2 hw/dma: sifive_pdma: reset Next* registers when Control.clai [...] adds 9a8c26c08c hw/dma: sifive_pdma: claim bit must be set before DMA transactions adds e22d90f5f9 hw/dma: sifive_pdma: allow non-multiple transaction size tra [...] adds ae000c5f65 hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transfer adds 758c07c9fc docs/system/riscv: sifive_u: Update U-Boot instructions adds c601354756 target/riscv: Backup/restore mstatus.SD bit when virtual reg [...] adds db70794ea8 target/riscv: csr: Rename HCOUNTEREN_CY and friends adds ed481d9837 hw/riscv: opentitan: Correct the USB Dev address adds 2c3e83f92d Merge remote-tracking branch 'remotes/alistair23/tags/pull-r [...] adds fd761337ac hw/nvme: fix validation of ASQ and ACQ adds 07a3dfa7c4 hw/nvme: fix verification of select field in namespace attachment adds c53a9a9102 hw/nvme: Return error for fused operations adds 73257aa023 Merge remote-tracking branch 'remotes/nvme/tags/nvme-next-pu [...] adds 1fb6a87d0b linux-user/aarch64: Set siginfo_t addr field for SIGTRAP signals adds 1af354120d linux-user/arm: Set siginfo_t addr field for SIGTRAP signals adds babe6d5c88 linux-user/arm: Use force_sig() to deliver fpa11 emulation SIGFPE adds 819121b9b0 linux-user: Zero out target_siginfo_t in force_sig() adds af7969605e linux-user: Provide new force_sig_fault() function adds 4c90f0ba9d linux-user/arm: Use force_sig_fault() adds fce9608d02 linux-user/aarch64: Use force_sig_fault() adds e749ea2479 Merge remote-tracking branch 'remotes/vivier2/tags/linux-use [...] adds 8b1d5b3c35 include/exec: Move cpu_signal_handler declaration adds 0596fa11f1 accel/tcg: Restrict cpu_handle_halt() to sysemu adds 10d4af5810 tcg/mips: Drop inline markers adds d7fc9f48c3 tcg/mips: Allow JAL to be out of range in tcg_out_bswap_subr adds 5a8f0a5dd2 tcg/mips: Unset TCG_TARGET_HAS_direct_jump adds 3d1e8ed011 tcg/mips: Drop special alignment for code_gen_buffer adds 897fd616fd tcg/sparc: Drop inline markers adds 220b2da7f3 tcg/sparc: Introduce tcg_out_mov_delay adds fa947a667f hw/core: Make do_unaligned_access noreturn adds 81c65ee223 tcg/riscv: Remove add with zero on user-only memory access adds 11a1199846 Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-2021 [...]
No new revisions were added by this update.
Summary of changes: MAINTAINERS | 5 + accel/hvf/hvf-accel-ops.c | 21 +- accel/tcg/cpu-exec.c | 6 +- contrib/elf2dmp/download.c | 22 +- contrib/elf2dmp/pdb.c | 4 + docs/system/riscv/sifive_u.rst | 50 +- docs/system/riscv/virt.rst | 10 + hw/dma/sifive_pdma.c | 54 +- hw/intc/Kconfig | 2 +- hw/intc/arm_gicv3_cpuif.c | 5 +- hw/intc/ibex_plic.c | 17 +- hw/intc/meson.build | 2 +- hw/intc/riscv_aclint.c | 460 +++++++ hw/intc/sifive_clint.c | 287 ----- hw/intc/sifive_plic.c | 30 +- hw/nvme/ctrl.c | 31 +- hw/nvme/trace-events | 2 - hw/riscv/Kconfig | 13 +- hw/riscv/microchip_pfsoc.c | 13 +- hw/riscv/opentitan.c | 13 +- hw/riscv/shakti_c.c | 16 +- hw/riscv/sifive_e.c | 15 +- hw/riscv/sifive_u.c | 68 +- hw/riscv/spike.c | 16 +- hw/riscv/virt.c | 654 ++++++---- hw/timer/Kconfig | 3 + hw/timer/ibex_timer.c | 17 +- hw/timer/meson.build | 1 + hw/timer/sifive_pwm.c | 468 +++++++ hw/timer/trace-events | 6 + include/block/nvme.h | 5 + include/exec/exec-all.h | 13 + include/hw/core/tcg-cpu-ops.h | 3 +- include/hw/intc/ibex_plic.h | 2 + include/hw/intc/riscv_aclint.h | 80 ++ include/hw/intc/sifive_clint.h | 60 - include/hw/intc/sifive_plic.h | 4 + include/hw/riscv/sifive_u.h | 14 +- include/hw/riscv/virt.h | 2 + include/hw/timer/ibex_timer.h | 2 + .../stm32f4xx_syscfg.h => timer/sifive_pwm.h} | 48 +- include/sysemu/hvf_int.h | 12 +- linux-user/aarch64/cpu_loop.c | 32 +- linux-user/arm/cpu_loop.c | 63 +- linux-user/signal-common.h | 1 + linux-user/signal.c | 19 +- meson.build | 8 + target/alpha/cpu.h | 10 +- target/arm/cpu.c | 56 +- target/arm/cpu.h | 13 +- target/arm/helper.c | 77 +- target/arm/hvf/hvf.c | 1278 ++++++++++++++++++++ target/arm/hvf/meson.build | 3 + target/arm/hvf/trace-events | 11 + target/arm/hvf_arm.h | 18 + target/arm/internals.h | 46 +- target/arm/kvm_arm.h | 2 - target/arm/machine.c | 13 + target/arm/meson.build | 2 + target/arm/translate-m-nocp.c | 8 +- target/arm/translate-mve.c | 310 +++-- target/arm/translate-vfp.c | 33 +- target/arm/translate.c | 42 +- target/arm/translate.h | 2 + target/avr/cpu.h | 2 - target/cris/cpu.h | 8 - target/hexagon/cpu.h | 3 - target/hppa/cpu.c | 7 +- target/hppa/cpu.h | 3 - target/i386/cpu.h | 7 - target/i386/hvf/hvf.c | 11 + target/m68k/cpu.h | 8 - target/microblaze/cpu.h | 9 +- target/mips/cpu.h | 3 - target/mips/internal.h | 2 - target/mips/tcg/tcg-internal.h | 4 +- target/nios2/cpu.h | 6 +- target/openrisc/cpu.h | 2 - target/ppc/cpu.h | 7 - target/ppc/internal.h | 4 +- target/riscv/cpu.c | 31 + target/riscv/cpu.h | 4 +- target/riscv/cpu_bits.h | 12 +- target/riscv/cpu_helper.c | 3 +- target/riscv/csr.c | 26 +- target/rx/cpu.h | 4 - target/s390x/cpu.h | 7 - target/s390x/s390x-internal.h | 4 +- target/sh4/cpu.h | 7 +- target/sparc/cpu.h | 2 - target/tricore/cpu.h | 2 - target/xtensa/cpu.h | 6 +- tcg/mips/tcg-target.c.inc | 105 +- tcg/mips/tcg-target.h | 12 +- tcg/region.c | 91 -- tcg/riscv/tcg-target.c.inc | 10 +- tcg/sparc/tcg-target.c.inc | 64 +- 97 files changed, 3822 insertions(+), 1257 deletions(-) create mode 100644 hw/intc/riscv_aclint.c delete mode 100644 hw/intc/sifive_clint.c create mode 100644 hw/timer/sifive_pwm.c create mode 100644 include/hw/intc/riscv_aclint.h delete mode 100644 include/hw/intc/sifive_clint.h copy include/hw/{misc/stm32f4xx_syscfg.h => timer/sifive_pwm.h} (60%) create mode 100644 target/arm/hvf/hvf.c create mode 100644 target/arm/hvf/meson.build create mode 100644 target/arm/hvf/trace-events create mode 100644 target/arm/hvf_arm.h