[Tcwg-commits] [toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-next-allyesconfig updated (e5dd30f77e1 -> 977205b595c)

23 Oct 2019


      This is an automated email from the git hooks/post-receive script.
tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-next-allyesconfig
in repository toolchain/ci/llvm-project.
from  e5dd30f77e1 [ThinLTO] Add code comment. NFC
      adds  e4af9de36ca [MIPS GlobalISel] Select MSA vector generic and builtin add
      adds  95290827d7d [MIParser] Set RegClassOrRegBank during instruction parsing
      adds  3ef017d0669 [InstCombine] Signed saturation tests. NFC
      adds  40c47680eb2     [libcxx] Remove shared_ptr::make_shared
      adds  186155b89c2 [InstCombine] Signed saturation patterns
      adds  3bf7fddeb05 Update git-llvm script to push to GitHub
      adds  0bff9bd26e3 [lldb] Adjust for the new class_rw_t layout.
      adds  19ca80ef057 gn build: make sync build work with git revs now that svn is gone
      adds  48f57138be5 [AMDGPU] Allow tied operand subreg folding
      adds  8be5827f856 Test commit - add clarification to README regarding Darwin.
      adds  a7cebfe9c03 Relax assertions when there's really no entries. [NFC]
      adds  f9b1dc5553c [AMDGPU] Updated fold-vgpr-copy.mir test. NFC.
      adds  9b1419a9e50 [NFC][LVI][CVP] Tests where pre-specified `add` no-wrap fla [...]
      adds  4334892e7b0 [DAGCombine][ARM] x ==/!= c  ->  (x - c) ==/!= 0  iff '-c'  [...]
      adds  68f5ca4e19c [HIP] Add option -fgpu-allow-device-init
      adds  aed9d6d64a3 [RISCV] Add support for -ffixed-xX flags
      adds  e0e7d06df3e fix a few typos to test git committing
      adds  70316d3174d Revert "Fix lld detection in standalone compiler-rt."
      adds  1c98ff49a30 Fix name of warn_ignored_hip_only_option
      adds  4c539e8da1b Revert r374202"[ObjC generics] Fix not inheriting type boun [...]
      adds  f86dc64bad4 typo fix test commit
      adds  cf57be9d349 [PowerPC][NFC] Remove deprecated Function Attrs comments
      adds  efd7caaa4ec Fix broken sphinx link in CMake.rst.
      adds  31d3c1d8b70 [PowerPC][NFC] Remove deprecated Function Attrs comments #2
      adds  19e95ab4210 [NFC] Strip trailing whitespace in test to test Github committing
      adds  437e0e5191c [libcxx][test][NFC] Fix comment typos.
      adds  d052a578de5 [c++2a] Allow comparison functions to be explicitly defaulted.
      adds  20bf0cf2f02 [TargetLowering] optimizeSetCCToComparisonWithZero(): add e [...]
      adds  c46d24f5c31 [MIPS GlobalISel] Select MSA vector generic and builtin sub
      adds  d1815dacb00 [MIPS GlobalISel] Select MSA vector generic and builtin mul
      adds  64df708400a [lib/ObjectYAML] - Add a full stop to the comment. NFC.
      adds  74a72e68484 [DebugInfo] Stop describing imms in TargetInstrInfo's descr [...]
      adds  4b63ca1379a [Mips] Use appropriate private label prefix based on Mips ABI
      adds  40668abca4d [Support] Add a way to run a function on a detached thread
       new  7bc7fe6b789 Revert "[Support] Add a way to run a function on a detached [...]
       new  977205b595c [Sanitizers] Add support for RISC-V 64-bit
The 2 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails.  The revisions
listed as "adds" were already present in the repository and have only
been added to this reference.
Summary of changes:
 clang/include/clang/AST/Decl.h                     |   7 +
 clang/include/clang/AST/Type.h                     |   2 +-
 clang/include/clang/Basic/DiagnosticCommonKinds.td |   8 +-
 clang/include/clang/Basic/DiagnosticGroups.td      |   4 +
 clang/include/clang/Basic/DiagnosticSemaKinds.td   |  25 +
 clang/include/clang/Basic/LangOptions.def          |   1 +
 clang/include/clang/Driver/Options.td              |   9 +-
 clang/include/clang/Sema/Sema.h                    |  73 ++-
 clang/lib/AST/Decl.cpp                             |  23 +-
 clang/lib/AST/Type.cpp                             |   4 -
 clang/lib/CodeGen/CGDeclCXX.cpp                    |   7 +-
 clang/lib/Driver/ToolChains/Arch/RISCV.cpp         |  64 +++
 clang/lib/Driver/ToolChains/HIP.cpp                |   4 +
 clang/lib/Frontend/CompilerInvocation.cpp          |   7 +
 clang/lib/Parse/ParseDecl.cpp                      |   3 +-
 clang/lib/Parse/ParseDeclCXX.cpp                   |   3 +-
 clang/lib/Parse/ParseStmtAsm.cpp                   |   7 +-
 clang/lib/Sema/SemaCUDA.cpp                        |   2 +
 clang/lib/Sema/SemaDecl.cpp                        |  22 -
 clang/lib/Sema/SemaDeclCXX.cpp                     | 285 ++++++++++--
 clang/lib/Sema/SemaTemplateInstantiateDecl.cpp     |   9 +-
 .../class.compare/class.compare.default/p1.cpp     |  46 ++
 clang/test/CXX/class/class.compare/class.eq/p1.cpp |  25 +
 .../test/CXX/class/class.compare/class.rel/p1.cpp  |  25 +
 .../dcl.fct.def/dcl.fct.def.default/p1.cpp         |  26 +-
 clang/test/CodeGenCUDA/device-init-fun.cu          |  19 +
 clang/test/Driver/riscv-fixed-x-register.c         | 341 ++++++++++++++
 clang/test/Frontend/warn-device-init-fun.cu        |   8 +
 clang/test/Parser/cxx0x-decl.cpp                   |   2 +-
 clang/test/SemaCXX/cxx0x-defaulted-functions.cpp   |   2 +-
 clang/test/SemaCXX/cxx17-compat.cpp                |  33 ++
 clang/test/SemaObjC/parameterized_classes_subst.m  |  14 -
 clang/tools/driver/cc1as_main.cpp                  |   5 +-
 compiler-rt/CMakeLists.txt                         |   2 +-
 compiler-rt/cmake/config-ix.cmake                  |   5 +-
 .../lib/sanitizer_common/sanitizer_linux.cpp       |  10 +-
 .../lib/sanitizer_common/sanitizer_platform.h      |   8 +-
 .../sanitizer_platform_limits_linux.cpp            |   2 +-
 .../sanitizer_platform_limits_posix.cpp            |   2 +-
 .../sanitizer_platform_limits_posix.h              |   3 +
 libcxx/include/memory                              |  45 +-
 .../memory/aligned_allocation_macro.pass.cpp       |   2 +-
 .../array/array.cons/initializer_list.pass.cpp     |   2 +-
 .../lexically_relative_and_proximate.pass.cpp      |   2 +-
 .../fs.op.funcs/fs.op.relative/relative.pass.cpp   |   2 +-
 .../weakly_canonical.pass.cpp                      |   2 +-
 .../fpos/fpos.operations/difference.pass.cpp       |   2 +-
 .../fpos/fpos.operations/subtraction.pass.cpp      |   2 +-
 libcxx/test/std/numerics/c.math/abs.pass.cpp       |   4 +-
 .../string_compare/size_size_string_view.pass.cpp  |   2 +-
 .../opge.string_view.pointer.pass.cpp              |   4 +-
 .../opgt.string_view.pointer.pass.cpp              |   4 +-
 .../ople.string_view.pointer.pass.cpp              |   4 +-
 .../oplt.string_view.pointer.pass.cpp              |   4 +-
 .../meta.const.eval/is_constant_evaluated.pass.cpp |   2 +-
 .../meta/meta.rel/is_convertible.pass.cpp          |   2 +-
 .../optional/optional.specalg/swap.pass.cpp        |   2 +-
 .../unique.ptr.asgn/move_convert.pass.cpp          |   2 +-
 .../unique.ptr.class/unique.ptr.ctor/move.pass.cpp |   4 +-
 .../unique.ptr.ctor/move_convert.pass.cpp          |   2 +-
 .../unique.ptr.ctor/nullptr.pass.cpp               |   2 +-
 .../unique.ptr.ctor/pointer.pass.cpp               |   2 +-
 .../time.cal.weekday.members/ok.pass.cpp           |   2 +-
 .../tuple.tuple/tuple.assign/convert_copy.pass.cpp |   2 +-
 .../tuple.tuple/tuple.assign/convert_move.pass.cpp |   2 +-
 lld/include/lld/Core/Error.h                       |   4 +-
 lld/include/lld/Core/UndefinedAtom.h               |   2 +-
 .../Disassembler/llvm/DisassemblerLLVMC.cpp        |   6 +-
 .../Instruction/MIPS/EmulateInstructionMIPS.cpp    |   5 +-
 .../MIPS64/EmulateInstructionMIPS64.cpp            |   9 +-
 .../AppleObjCClassDescriptorV2.cpp                 |  12 +
 llvm/docs/CMake.rst                                |   2 +-
 llvm/include/llvm/CodeGen/TargetLowering.h         |   7 +
 llvm/include/llvm/Support/TargetRegistry.h         |  15 +-
 llvm/lib/CodeGen/LLVMTargetMachine.cpp             |   4 +-
 llvm/lib/CodeGen/MIRParser/MIParser.cpp            |   2 +
 llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp   |  65 +++
 llvm/lib/CodeGen/TargetInstrInfo.cpp               |   3 -
 llvm/lib/MC/MCDisassembler/Disassembler.cpp        |   5 +-
 llvm/lib/Object/ModuleSymbolTable.cpp              |   4 +-
 llvm/lib/ObjectYAML/ELFEmitter.cpp                 |   2 +-
 .../AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp   |   3 +-
 .../Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp |   4 +-
 .../Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.h   |   2 +-
 llvm/lib/Target/AMDGPU/SIFoldOperands.cpp          |  12 -
 .../Target/ARC/MCTargetDesc/ARCMCTargetDesc.cpp    |   3 +-
 .../Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp    |   3 +-
 llvm/lib/Target/AVR/MCTargetDesc/AVRMCAsmInfo.cpp  |   2 +-
 llvm/lib/Target/AVR/MCTargetDesc/AVRMCAsmInfo.h    |   2 +-
 llvm/lib/Target/BPF/MCTargetDesc/BPFMCAsmInfo.h    |   2 +-
 .../Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp   |   3 +-
 .../Target/Lanai/MCTargetDesc/LanaiMCAsmInfo.cpp   |   3 +-
 .../lib/Target/Lanai/MCTargetDesc/LanaiMCAsmInfo.h |   3 +-
 .../Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.cpp |   3 +-
 .../Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.h   |   2 +-
 .../lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp |  18 +-
 llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h  |   3 +-
 .../Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp  |   5 +-
 llvm/lib/Target/Mips/MipsInstructionSelector.cpp   |   4 +-
 llvm/lib/Target/Mips/MipsLegalizerInfo.cpp         |  74 ++-
 llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp      |  10 +-
 .../Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.cpp   |   3 +-
 .../lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.h |   3 +-
 .../PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp       |   3 +-
 llvm/lib/Target/PowerPC/README.txt                 |   3 +
 .../RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp       |   3 +-
 llvm/lib/Target/RISCV/RISCV.td                     |   5 +
 llvm/lib/Target/RISCV/RISCVFrameLowering.cpp       |  11 +
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp        |  38 ++
 llvm/lib/Target/RISCV/RISCVISelLowering.h          |   6 +
 llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp        |  11 +
 llvm/lib/Target/RISCV/RISCVRegisterInfo.h          |   2 +
 llvm/lib/Target/RISCV/RISCVSubtarget.cpp           |   1 +
 llvm/lib/Target/RISCV/RISCVSubtarget.h             |   5 +
 .../Sparc/MCTargetDesc/SparcMCTargetDesc.cpp       |   6 +-
 .../SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp   |   3 +-
 .../MCTargetDesc/WebAssemblyMCAsmInfo.cpp          |   3 +-
 .../MCTargetDesc/WebAssemblyMCAsmInfo.h            |   3 +-
 .../MCTargetDesc/WebAssemblyMCTargetDesc.cpp       |   5 +-
 .../Target/X86/MCTargetDesc/X86MCTargetDesc.cpp    |   3 +-
 llvm/lib/Target/X86/X86InstrInfo.cpp               |   5 +
 .../XCore/MCTargetDesc/XCoreMCTargetDesc.cpp       |   3 +-
 .../Transforms/InstCombine/InstCombineInternal.h   |   1 +
 .../Transforms/InstCombine/InstCombineSelect.cpp   |  67 +++
 llvm/test/CodeGen/AMDGPU/fold-vgpr-copy.mir        |  35 +-
 llvm/test/CodeGen/ARM/addsubcarry-promotion.ll     |  62 +--
 llvm/test/CodeGen/MIR/Mips/setRegClassOrRegBank.ll |  27 ++
 .../test/CodeGen/MIR/Mips/setRegClassOrRegBank.mir |  39 ++
 .../Mips/GlobalISel/instruction-select/add_vec.mir | 130 ++++++
 .../Mips/GlobalISel/instruction-select/mul_vec.mir | 130 ++++++
 .../Mips/GlobalISel/instruction-select/sub_vec.mir | 130 ++++++
 .../CodeGen/Mips/GlobalISel/legalizer/add_vec.mir  | 122 +++++
 .../Mips/GlobalISel/legalizer/add_vec_builtin.mir  | 237 ++++++++++
 .../CodeGen/Mips/GlobalISel/legalizer/mul_vec.mir  | 122 +++++
 .../Mips/GlobalISel/legalizer/mul_vec_builtin.mir  | 129 ++++++
 .../GlobalISel/legalizer/sitofp_and_uitofp.mir     |  20 +-
 .../CodeGen/Mips/GlobalISel/legalizer/sub_vec.mir  | 122 +++++
 .../Mips/GlobalISel/legalizer/sub_vec_builtin.mir  | 237 ++++++++++
 .../CodeGen/Mips/GlobalISel/llvm-ir/add_vec.ll     |  70 +++
 .../Mips/GlobalISel/llvm-ir/add_vec_builtin.ll     | 138 ++++++
 .../CodeGen/Mips/GlobalISel/llvm-ir/mul_vec.ll     |  70 +++
 .../Mips/GlobalISel/llvm-ir/mul_vec_builtin.ll     |  74 +++
 .../CodeGen/Mips/GlobalISel/llvm-ir/sub_vec.ll     |  70 +++
 .../Mips/GlobalISel/llvm-ir/sub_vec_builtin.ll     | 138 ++++++
 .../Mips/GlobalISel/regbankselect/add_vec.mir      | 126 +++++
 .../Mips/GlobalISel/regbankselect/mul_vec.mir      | 126 +++++
 .../Mips/GlobalISel/regbankselect/sub_vec.mir      | 126 +++++
 .../CodeGen/Mips/compactbranches/no-beqzc-bnezc.ll |   4 +-
 llvm/test/CodeGen/PowerPC/build-vector-tests.ll    | 131 +-----
 llvm/test/CodeGen/PowerPC/sms-simple.ll            |   6 +-
 llvm/test/CodeGen/RISCV/reserved-reg-errors.ll     |  36 ++
 llvm/test/CodeGen/RISCV/reserved-regs.ll           | 130 ++++++
 llvm/test/CodeGen/X86/pr43769.ll                   |  54 +++
 llvm/test/DebugInfo/MIR/SystemZ/call-site-lzer.mir |  83 ++++
 .../MIR}/SystemZ/lit.local.cfg                     |   0
 llvm/test/MC/Mips/macro-li.d.s                     |  26 +-
 llvm/test/MC/Mips/macro-li.s.s                     |  12 +-
 llvm/test/MC/Mips/private-prefix.s                 |  22 +
 .../Transforms/CorrelatedValuePropagation/icmp.ll  | 136 ++++++
 llvm/test/Transforms/InstCombine/sadd_sat.ll       | 503 ++++++++++++++++++++
 llvm/tools/dsymutil/DwarfStreamer.cpp              |   4 +-
 llvm/tools/llvm-cfi-verify/lib/FileAnalysis.cpp    |   5 +-
 llvm/tools/llvm-dwp/llvm-dwp.cpp                   |   5 +-
 llvm/tools/llvm-exegesis/lib/Analysis.cpp          |   5 +-
 llvm/tools/llvm-jitlink/llvm-jitlink.cpp           |   5 +-
 .../llvm-mc-assemble-fuzzer.cpp                    |   6 +-
 llvm/tools/llvm-mc/Disassembler.cpp                |   6 +-
 llvm/tools/llvm-mc/Disassembler.h                  |   3 +-
 llvm/tools/llvm-mc/llvm-mc.cpp                     |   5 +-
 llvm/tools/llvm-mca/llvm-mca.cpp                   |   4 +-
 llvm/tools/llvm-objdump/MachODump.cpp              |  10 +-
 llvm/tools/llvm-objdump/llvm-objdump.cpp           |   4 +-
 llvm/tools/llvm-rtdyld/llvm-rtdyld.cpp             |   5 +-
 llvm/tools/sancov/sancov.cpp                       |   4 +-
 llvm/unittests/DebugInfo/DWARF/DwarfGenerator.cpp  |   4 +-
 .../ExecutionEngine/JITLink/JITLinkTestCommon.cpp  |   4 +-
 llvm/unittests/MC/DwarfLineTables.cpp              |   4 +-
 llvm/unittests/MC/MCInstPrinter.cpp                |   4 +-
 llvm/utils/TableGen/SequenceToOffsetTable.h        |   4 +-
 llvm/utils/git-svn/git-llvm                        | 510 ++++-----------------
 .../utils/gn/build/sync_source_lists_from_cmake.py |  24 +-
 181 files changed, 5034 insertions(+), 967 deletions(-)
 create mode 100644 clang/test/CXX/class/class.compare/class.compare.default/p1.cpp
 create mode 100644 clang/test/CXX/class/class.compare/class.eq/p1.cpp
 create mode 100644 clang/test/CXX/class/class.compare/class.rel/p1.cpp
 create mode 100644 clang/test/CodeGenCUDA/device-init-fun.cu
 create mode 100644 clang/test/Driver/riscv-fixed-x-register.c
 create mode 100644 clang/test/Frontend/warn-device-init-fun.cu
 create mode 100644 llvm/test/CodeGen/MIR/Mips/setRegClassOrRegBank.ll
 create mode 100644 llvm/test/CodeGen/MIR/Mips/setRegClassOrRegBank.mir
 create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/instruction-select/add_vec.mir
 create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/instruction-select/mul_vec.mir
 create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/instruction-select/sub_vec.mir
 create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/legalizer/add_vec.mir
 create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/legalizer/add_vec_builtin.mir
 create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul_vec.mir
 create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul_vec_builtin.mir
 create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub_vec.mir
 create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub_vec_builtin.mir
 create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add_vec.ll
 create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add_vec_builtin.ll
 create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/mul_vec.ll
 create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/mul_vec_builtin.ll
 create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sub_vec.ll
 create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sub_vec_builtin.ll
 create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/regbankselect/add_vec.mir
 create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/regbankselect/mul_vec.mir
 create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sub_vec.mir
 create mode 100644 llvm/test/CodeGen/RISCV/reserved-reg-errors.ll
 create mode 100644 llvm/test/CodeGen/RISCV/reserved-regs.ll
 create mode 100644 llvm/test/CodeGen/X86/pr43769.ll
 create mode 100644 llvm/test/DebugInfo/MIR/SystemZ/call-site-lzer.mir
 copy llvm/test/{Analysis/CostModel => DebugInfo/MIR}/SystemZ/lit.local.cfg (100%)
 create mode 100644 llvm/test/MC/Mips/private-prefix.s
 create mode 100644 llvm/test/Transforms/InstCombine/sadd_sat.ll
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[Tcwg-commits] [toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-next-allyesconfig updated (e5dd30f77e1 -> 977205b595c)