This is an automated email from the git hooks/post-receive script.
tcwg-benchmark pushed a change to branch linaro-local/ci/tcwg_bmk_stm32/gnu_eabi-release-arm-eabi-coremark-Os in repository toolchain/ci/gcc.
from a27067c70b7 Put PREFETCHW back to march=broadwell adds 6abef270285 Daily bump. adds c52868904b7 PR target/97682 - Fix to reuse t1 register between call add [...] adds 9d65095e725 AArch64: Fix overflow in memcopy expansion on aarch64. adds 7e785f4c764 AArch64: Skip test for pr97535 on ILP32 since it can't expr [...] adds cbc9dab25fb libstdc++: Make pmr::synchronized_pool_resource work withou [...] adds 600ef5614b2 add --with-tune configure flag adds e56eee08489 add --with-{cpu,arch,tune}-{32,64} as alias flags for --wit [...] adds 83ded159c96 Daily bump. adds 9c78c3426be Daily bump.
No new revisions were added by this update.
Summary of changes: gcc/ChangeLog | 45 ++++++ gcc/DATESTAMP | 2 +- gcc/config.gcc | 23 ++- gcc/config/aarch64/aarch64.c | 13 +- gcc/config/riscv/riscv.c | 23 +-- gcc/config/riscv/riscv.h | 6 +- gcc/doc/install.texi | 2 +- gcc/testsuite/ChangeLog | 26 ++++ gcc/testsuite/g++.target/riscv/pr97682.C | 160 +++++++++++++++++++++ gcc/testsuite/gcc.target/aarch64/pr97535.c | 16 +++ gcc/testsuite/gcc.target/riscv/interrupt-3.c | 4 +- gcc/testsuite/gcc.target/riscv/interrupt-4.c | 4 +- libstdc++-v3/ChangeLog | 27 ++++ libstdc++-v3/src/c++17/memory_resource.cc | 127 ++++++++++------ .../synchronized_pool_resource/allocate_single.cc | 24 ++++ .../synchronized_pool_resource/cons_single.cc | 24 ++++ .../synchronized_pool_resource/release_single.cc | 24 ++++ 17 files changed, 481 insertions(+), 69 deletions(-) create mode 100644 gcc/testsuite/g++.target/riscv/pr97682.C create mode 100644 gcc/testsuite/gcc.target/aarch64/pr97535.c create mode 100644 libstdc++-v3/testsuite/20_util/synchronized_pool_resource/alloc [...] create mode 100644 libstdc++-v3/testsuite/20_util/synchronized_pool_resource/cons_ [...] create mode 100644 libstdc++-v3/testsuite/20_util/synchronized_pool_resource/relea [...]