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from 06d4ac89d73 [AArch64][AsmParser] Extend RegOp with integrated 'shift/extend'. new 1e2a2ae6dec [Sparc] Use synthetic instruction clr to zero register inst [...]
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Summary of changes: lib/Target/Sparc/SparcInstrInfo.td | 3 +++ test/CodeGen/SPARC/atomics.ll | 5 ++-- test/CodeGen/SPARC/imm.ll | 46 ++++++++++++++++++++++++++++++++ test/CodeGen/SPARC/inlineasm.ll | 2 +- test/CodeGen/SPARC/vector-extract-elt.ll | 2 +- 5 files changed, 54 insertions(+), 4 deletions(-) create mode 100644 test/CodeGen/SPARC/imm.ll