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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-next-allyesconfig in repository toolchain/ci/binutils-gdb.
from 2bf3b79d05 Search for DWZ files in debug-file-directories as well adds 12bf652539 Sync .gitignore with gcc adds 7ddfb1a891 Add gnu global outputs to .gitignore adds e450204220 gdb/riscv: place unknown csrs into the correct register groups adds 533b2ae07d gdb/riscv: remove csr aliases created with DECLARE_CSR_ALIAS adds 2542804022 gdb/riscv: rewrite target description validation, add rv32e support adds 5f410aa50c testsuite/ld-elf/pr26936.d: Pass -W. adds 317c8bbc29 Automatic date update in version.in adds c6162010ad [GOLD] PR26936 test adds 9a5c1ed81d VAX/LD/testsuite: Wrap excessively long lines adds b10b530a45 IBM Z: Add support for HLASM extended mnemonics
No new revisions were added by this update.
Summary of changes: .gitignore | 10 + ChangeLog | 8 + bfd/version.h | 2 +- gas/ChangeLog | 9 + gas/testsuite/gas/s390/esa-g5.d | 78 ++- gas/testsuite/gas/s390/esa-g5.s | 26 + gas/testsuite/gas/s390/esa-z900.d | 72 +- gas/testsuite/gas/s390/esa-z900.s | 23 + gas/testsuite/gas/s390/zarch-z900.d | 7 +- gas/testsuite/gas/s390/zarch-z900.s | 3 + gdb/ChangeLog | 62 ++ gdb/arch/riscv.c | 15 +- gdb/arch/riscv.h | 9 +- gdb/features/Makefile | 1 + gdb/features/riscv/{32bit-cpu.c => rv32e-xregs.c} | 20 +- .../riscv/{32bit-cpu.xml => rv32e-xregs.xml} | 16 - gdb/riscv-tdep.c | 755 ++++++++++++--------- gdb/riscv-tdep.h | 5 + gdb/testsuite/ChangeLog | 9 + gdb/testsuite/gdb.arch/riscv-tdesc-regs.exp | 41 +- gold/ChangeLog | 6 + gold/testsuite/Makefile.am | 8 +- gold/testsuite/Makefile.in | 8 +- ld/ChangeLog | 14 + ld/testsuite/ld-elf/pr26936.d | 2 +- ld/testsuite/ld-s390/tlsbin_64.dd | 10 +- ld/testsuite/ld-vax-elf/vax-elf.exp | 9 +- opcodes/ChangeLog | 4 + opcodes/s390-opc.txt | 14 + 29 files changed, 794 insertions(+), 452 deletions(-) copy gdb/features/riscv/{32bit-cpu.c => rv32e-xregs.c} (54%) copy gdb/features/riscv/{32bit-cpu.xml => rv32e-xregs.xml} (65%)