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from a0cc5eb21de RISC-V: Force scalable vector on all vsetvl tests new 2cd55480857 aarch64: Fix parens in aarch64_stp_reg_operand [PR113061] new 80e1375ed7a i386: Fix mmx.md signbit expanders [PR112816]
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Summary of changes: gcc/config/aarch64/predicates.md | 4 ++-- gcc/config/i386/mmx.md | 10 ++++++++-- .../gcc.target/i386/{sse2-pr112816.c => sse2-pr112816-2.c} | 2 +- gcc/testsuite/gfortran.dg/PR113061.f90 | 12 ++++++++++++ 4 files changed, 23 insertions(+), 5 deletions(-) copy gcc/testsuite/gcc.target/i386/{sse2-pr112816.c => sse2-pr112816-2.c} (95%) create mode 100644 gcc/testsuite/gfortran.dg/PR113061.f90