[Tcwg-commits] [gcc] branch master updated (c8e07c79514 -> 95dca4e7482)

26 Jan 2023


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unknown user pushed a change to branch master
in repository gcc.
from  c8e07c79514 Fortran: fix ICE in check_host_association [PR108544]
       new  f91cd98ebc3 RISC-V: Fix pointer tree type for store pointer.
       new  856eec0d6b6 RISC-V: Fix inferior codegen for vse intrinsics.
       new  91a41201b5c RISC-V: Fix vsetivli instruction asm for IMM AVL
       new  005fad9d251 RISC-V: Fix bugs for refine vsetvl a5, zero into vsetvl zer [...]
       new  011ba384b34 RISC-V: Fix wrong in_group flag in validate_change call function
       new  8d8cc482ea4 RISC-V: Fix backward_propagate_worthwhile_p
       new  aef20243b84 RISC-V: Simplify codes of changing vsetvl instruction
       new  cca9c44eca4 RISC-V: Fix bugs of available condition.
       new  387cd9d3795 RISC-V: Refine Phase 3 of VSETVL PASS
       new  cfe3fbc678d RISC-V: Cleanup the codes of bitmap create and free [NFC]
       new  00fb7698f0b RISC-V: Avoid redundant flow in forward fusion
       new  b9b251b7b95 RISC-V: Refine codes in backward fusion [NFC]
       new  27a2a4b6ed3 RISC-V: Rename insn into rinsn for rtx_insn * [NFC]
       new  7ae4d1dfb8f RISC-V: Remove dirty_pat since it is redundant
       new  acc10c79312 RISC-V: Add probability model of each block to prevent endl [...]
       new  4f673c5ee28 RISC-V: Fix bugs of supporting AVL=REG (single-real-def) in [...]
       new  6bc31c2c7c0 RISC-V: Add testcases for IMM (0 ~ 31) AVL
       new  cb31b22751e RISC-V: Add testcases for AVL=REG support
       new  95dca4e7482 RISC-V: Use get_typenode_from_name to get fixed-width integ [...]
The 19 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails.  The revisions
listed as "adds" were already present in the repository and have only
been added to this reference.
Summary of changes:
 gcc/config/riscv/riscv-vector-builtins-bases.cc    |    2 +-
 gcc/config/riscv/riscv-vector-builtins.cc          |   41 +-
 gcc/config/riscv/riscv-vector-builtins.def         |   78 +-
 gcc/config/riscv/riscv-vector-builtins.h           |    8 +-
 gcc/config/riscv/riscv-vsetvl.cc                   | 1335 ++++++++++++++------
 gcc/config/riscv/riscv-vsetvl.h                    |   86 +-
 gcc/config/riscv/vector.md                         |   25 +-
 .../gcc.target/riscv/rvv/base/vle-constraint-1.c   |   12 +-
 .../gcc.target/riscv/rvv/base/vse-constraint-1.c   |   97 ++
 .../gcc.target/riscv/rvv/vsetvl/avl_single-1.c     |   17 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-10.c    |   21 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-11.c    |   21 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-12.c    |   19 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-13.c    |   28 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-14.c    |   27 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-15.c    |   27 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-16.c    |   32 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-17.c    |   29 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-18.c    |   29 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-19.c    |   40 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-2.c     |   18 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-20.c    |   40 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-21.c    |   32 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-22.c    |   42 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-23.c    |   34 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-24.c    |   36 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-25.c    |   38 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-26.c    |   35 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-27.c    |   36 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-28.c    |   30 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-29.c    |   31 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-3.c     |   19 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-30.c    |   29 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-31.c    |   27 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-32.c    |   27 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-33.c    |   29 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-34.c    |   28 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-35.c    |   27 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-36.c    |   25 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-37.c    |   29 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-38.c    |   57 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-39.c    |   19 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-4.c     |   21 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-40.c    |   17 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-41.c    |   19 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-42.c    |   15 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-43.c    |   16 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-44.c    |   19 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-45.c    |   19 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-46.c    |   25 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-47.c    |   35 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-48.c    |   32 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-49.c    |   32 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-5.c     |   18 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-50.c    |   23 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-51.c    |   25 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-52.c    |   34 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-53.c    |   31 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-54.c    |   32 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-55.c    |   38 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-56.c    |   38 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-57.c    |   43 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-58.c    |   43 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-59.c    |   31 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-6.c     |   22 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-60.c    |   30 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-61.c    |   24 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-62.c    |   24 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-63.c    |   24 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-64.c    |   41 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-65.c    |   33 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-66.c    |   46 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-67.c    |   26 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-68.c    |   25 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-69.c    |   40 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-7.c     |   17 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-70.c    |   41 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-71.c    |   54 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-8.c     |   18 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-9.c     |   56 +
 .../gcc.target/riscv/rvv/vsetvl/imm_bb_prop-1.c    |   32 +
 .../gcc.target/riscv/rvv/vsetvl/imm_bb_prop-10.c   |   42 +
 .../gcc.target/riscv/rvv/vsetvl/imm_bb_prop-11.c   |   42 +
 .../gcc.target/riscv/rvv/vsetvl/imm_bb_prop-12.c   |   31 +
 .../gcc.target/riscv/rvv/vsetvl/imm_bb_prop-13.c   |   29 +
 .../gcc.target/riscv/rvv/vsetvl/imm_bb_prop-2.c    |   29 +
 .../gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c    |   22 +
 .../gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c    |   25 +
 .../gcc.target/riscv/rvv/vsetvl/imm_bb_prop-5.c    |   33 +
 .../gcc.target/riscv/rvv/vsetvl/imm_bb_prop-6.c    |   30 +
 .../gcc.target/riscv/rvv/vsetvl/imm_bb_prop-7.c    |   31 +
 .../gcc.target/riscv/rvv/vsetvl/imm_bb_prop-8.c    |   37 +
 .../gcc.target/riscv/rvv/vsetvl/imm_bb_prop-9.c    |   37 +
 .../gcc.target/riscv/rvv/vsetvl/imm_conflict-1.c   |   22 +
 .../gcc.target/riscv/rvv/vsetvl/imm_conflict-2.c   |   22 +
 .../gcc.target/riscv/rvv/vsetvl/imm_conflict-3.c   |   26 +
 .../gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c   |   38 +
 .../gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c   |   45 +
 .../riscv/rvv/vsetvl/imm_loop_invariant-1.c        |  195 +++
 .../riscv/rvv/vsetvl/imm_loop_invariant-10.c       |   41 +
 .../riscv/rvv/vsetvl/imm_loop_invariant-11.c       |   41 +
 .../riscv/rvv/vsetvl/imm_loop_invariant-12.c       |   28 +
 .../riscv/rvv/vsetvl/imm_loop_invariant-13.c       |   30 +
 .../riscv/rvv/vsetvl/imm_loop_invariant-14.c       |   31 +
 .../riscv/rvv/vsetvl/imm_loop_invariant-15.c       |   32 +
 .../riscv/rvv/vsetvl/imm_loop_invariant-16.c       |   29 +
 .../riscv/rvv/vsetvl/imm_loop_invariant-17.c       |   22 +
 .../riscv/rvv/vsetvl/imm_loop_invariant-2.c        |  168 +++
 .../riscv/rvv/vsetvl/imm_loop_invariant-3.c        |  141 +++
 .../riscv/rvv/vsetvl/imm_loop_invariant-4.c        |   77 ++
 .../riscv/rvv/vsetvl/imm_loop_invariant-5.c        |  114 ++
 .../riscv/rvv/vsetvl/imm_loop_invariant-6.c        |   64 +
 .../riscv/rvv/vsetvl/imm_loop_invariant-7.c        |   39 +
 .../riscv/rvv/vsetvl/imm_loop_invariant-8.c        |   45 +
 .../riscv/rvv/vsetvl/imm_loop_invariant-9.c        |   41 +
 .../gcc.target/riscv/rvv/vsetvl/imm_switch-1.c     |   22 +
 .../gcc.target/riscv/rvv/vsetvl/imm_switch-2.c     |   28 +
 .../gcc.target/riscv/rvv/vsetvl/imm_switch-3.c     |  189 +++
 .../gcc.target/riscv/rvv/vsetvl/imm_switch-4.c     |   26 +
 .../gcc.target/riscv/rvv/vsetvl/imm_switch-5.c     |   29 +
 .../gcc.target/riscv/rvv/vsetvl/imm_switch-6.c     |   30 +
 .../gcc.target/riscv/rvv/vsetvl/imm_switch-7.c     |   29 +
 .../gcc.target/riscv/rvv/vsetvl/imm_switch-8.c     |   35 +
 .../gcc.target/riscv/rvv/vsetvl/imm_switch-9.c     |   47 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-27.c          |    4 +-
 .../riscv/rvv/vsetvl/vlmax_back_prop-28.c          |    4 +-
 .../riscv/rvv/vsetvl/vlmax_back_prop-45.c          |    2 +-
 .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-25.c |   14 +-
 .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-26.c |   12 +-
 .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-27.c |   12 +-
 .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-28.c |    2 +-
 .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c  |    2 +-
 .../gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c |    1 -
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-12.c       |    2 +-
 134 files changed, 5514 insertions(+), 476 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vse-constraint-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-10.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-11.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-12.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-13.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-14.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-15.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-17.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-18.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-19.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-20.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-21.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-22.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-23.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-24.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-25.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-26.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-27.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-28.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-29.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-30.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-31.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-33.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-34.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-35.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-36.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-37.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-38.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-39.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-40.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-41.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-42.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-43.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-44.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-45.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-46.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-47.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-48.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-49.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-50.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-51.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-52.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-53.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-54.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-55.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-56.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-57.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-58.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-59.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-6.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-60.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-61.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-62.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-63.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-65.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-66.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-69.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-7.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-70.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-9.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-10.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-11.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-12.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-13.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-6.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-7.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-9.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-10.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-11.c
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[Tcwg-commits] [gcc] branch master updated (c8e07c79514 -> 95dca4e7482)