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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk/llvm-release-aarch64-spec2k6-O2 in repository toolchain/ci/llvm-project.
from 0489682ef3b Merging r360405: adds 836f1e2be4c Merging r359891: ------------------------------------------ [...] adds b73bafaff70 Correct test in r362634 adds c8af2415480 Merging r359898: ------------------------------------------ [...] adds 5b37d896a02 Merging r359899: ------------------------------------------ [...] adds d95b14d04ee Merging r360293: ------------------------------------------ [...] adds c493057bdee Merging r360439: adds 0462c73f761 Merging r360442: adds 4db27e1d1e1 Skip globals-fundamental test when Python is disabled adds 897fd6e1bb9 Merging r361237: adds e98c4c8cc77 Merging r355154: adds 0e657d45762 Merging r353905: adds ad5bcd4ee60 Merging r361090: adds 90c370c33dc Merging r351577: adds 9a2cfaed4eb Merging r358042: adds 213f2edbe61 Add release note for DIBuilder API changes adds 2fb27a25fcb Merging r360862:
No new revisions were added by this update.
Summary of changes: compiler-rt/lib/xray/tests/CMakeLists.txt | 5 +- libunwind/src/UnwindRegistersRestore.S | 238 +++++++++--------- libunwind/src/UnwindRegistersSave.S | 270 ++++++++++----------- libunwind/src/assembly.h | 2 - lld/ELF/InputSection.cpp | 4 - lld/ELF/Writer.cpp | 11 - lld/test/ELF/aarch64-cortex-a53-843419-tlsrelax.s | 4 +- lld/test/ELF/aarch64-tls-gdle.s | 4 +- lld/test/ELF/aarch64-tls-iele.s | 6 +- lld/test/ELF/aarch64-tls-le.s | 8 +- lld/test/ELF/aarch64-tlsld-ldst.s | 50 ++-- lld/test/ELF/arm-tls-le32.s | 12 +- lld/test/ELF/arm-tls-norelax-ie-le.s | 4 +- lld/test/ELF/gc-sections-metadata-startstop.s | 2 +- lld/test/ELF/mips-micro-relocs.s | 6 +- lld/test/ELF/mips-micror6-relocs.s | 4 +- .../SymbolFile/NativePDB/globals-fundamental.cpp | 2 +- llvm/docs/ReleaseNotes.rst | 20 ++ llvm/lib/MC/ELFObjectWriter.cpp | 1 + llvm/lib/MC/MCWin64EH.cpp | 2 +- llvm/lib/Target/AMDGPU/SIFoldOperands.cpp | 68 +++--- llvm/lib/Target/AMDGPU/VOP2Instructions.td | 12 +- .../PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp | 30 ++- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 4 +- llvm/lib/Target/Sparc/SparcRegisterInfo.cpp | 4 +- llvm/test/CodeGen/AMDGPU/add.ll | 83 ++----- .../ds-negative-offset-addressing-mode-loop.ll | 6 +- llvm/test/CodeGen/AMDGPU/fence-barrier.ll | 3 +- .../test/CodeGen/AMDGPU/fold-fi-operand-shrink.mir | 230 ++++++++++++++++++ .../AMDGPU/fold-immediate-operand-shrink.mir | 56 +++++ llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.ll | 3 +- llvm/test/CodeGen/AMDGPU/{add.ll => r600.add.ll} | 56 ----- llvm/test/CodeGen/AMDGPU/{sub.ll => r600.sub.ll} | 95 -------- llvm/test/CodeGen/AMDGPU/salu-to-valu.ll | 2 +- llvm/test/CodeGen/AMDGPU/sub.ll | 90 ++++--- llvm/test/CodeGen/SPARC/fp128.ll | 23 ++ llvm/test/MC/PowerPC/ppc64-localentry-symbols.s | 34 +++ .../test/tools/llvm-objdump/AMDGPU/source-lines.ll | 4 +- .../tools/llvm-objdump/elf-symbol-visibility.test | 37 +++ llvm/tools/llvm-objdump/llvm-objdump.cpp | 30 ++- 40 files changed, 877 insertions(+), 648 deletions(-) create mode 100644 llvm/test/CodeGen/AMDGPU/fold-fi-operand-shrink.mir copy llvm/test/CodeGen/AMDGPU/{add.ll => r600.add.ll} (75%) copy llvm/test/CodeGen/AMDGPU/{sub.ll => r600.sub.ll} (63%) create mode 100644 llvm/test/MC/PowerPC/ppc64-localentry-symbols.s create mode 100644 llvm/test/tools/llvm-objdump/elf-symbol-visibility.test