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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-defconfig in repository toolchain/ci/llvm-project.
from a30a4a35ecb Fix asan infinite loop on undefined symbol adds e97f2f33e75 build: allow the user to specify `llvm-tblgen` adds 7f0c23576f5 [NFC][Codegen][X86][AArch64] Add "(x s% C) == 0" tests adds 056640f8b31 [NFC][InstCombine] Add srem-by-signbit tests - still can fo [...] adds a2dd672c5ff [NFC][InstCombine] Autogenerate a few tests adds ae4c30a4bed [ELF] Support explicitly overriding relocation model in LTO adds ff22ec3d700 [Clang] Replace cc1 options '-mdisable-fp-elim' and '-momit [...] adds b9109562029 gn build: Merge r366622 adds b4e06328fc2 [lldb] Fix buildbot build fail caused by r366645 adds 8fabdfe9fcd [InstCombine] Don't use AddOne/SubOne to see if two APInts [...] adds 1d149d08d3a [InstCombine] Remove insertRangeTest code that handles the [...] adds fe1b8a09113 [NativePDB] Make GetOrCreateDeclForUid return an lldb CompilerDecl adds 8a431874e99 [NFC][InstCombine] Add a few extra srem-by-power-of-two tes [...] adds ca9dfdfaeca [lldb] Fix crash when looking up type coming from the Clang [...] adds c38899fc26e [ARM] Move MVE VPT block tests into the Thumb2 directory. NFC adds d7504a1569d [GISel]: Attach missing range metadata while translating G_LOADs adds 630be14ac64 [SmallBitVector] Fix bug in find_next_unset for small types [...] adds e6cd20ba534 [InstCombine] Update comment I missed in r366649. NFC
No new revisions were added by this update.
Summary of changes: clang/include/clang/Basic/CodeGenOptions.def | 5 +- clang/include/clang/Basic/CodeGenOptions.h | 6 + clang/include/clang/Driver/CC1Options.td | 4 +- clang/include/clang/Driver/Options.td | 2 +- clang/lib/CodeGen/CGCall.cpp | 21 +- clang/lib/Driver/ToolChains/Clang.cpp | 36 +- clang/lib/Frontend/CompilerInvocation.cpp | 29 +- clang/test/CodeGen/msp430-fp-elim.c | 2 +- clang/test/CodeGen/x86_64-profiling-keep-fp.c | 4 +- clang/test/CodeGen/xcore-abi.c | 3 +- clang/test/CodeGen/xcore-abi.cpp | 3 +- clang/test/CodeGenCXX/global-init.cpp | 5 +- clang/test/CodeGenObjCXX/msabi-stret.mm | 2 +- clang/test/Driver/cl-options.c | 18 +- clang/test/Driver/clang-translation.c | 2 +- clang/test/Driver/frame-pointer-elim.c | 20 +- clang/test/Driver/frame-pointer.c | 22 +- clang/test/Driver/woa-fp.c | 6 +- clang/test/Driver/xcore-opts.c | 3 +- lld/Common/TargetOptionsCommandFlags.cpp | 4 + lld/ELF/LTO.cpp | 4 +- lld/include/lld/Common/TargetOptionsCommandFlags.h | 1 + lld/test/ELF/lto/relocation-model.ll | 9 + lldb/cmake/modules/LLDBStandalone.cmake | 50 +- .../test/lang/objc/modules/TestObjCModules.py | 4 + .../Clang/ClangExpressionParser.cpp | 4 +- .../Clang/ClangModulesDeclVendor.cpp | 12 +- .../Plugins/SymbolFile/NativePDB/PdbAstBuilder.cpp | 16 +- .../Plugins/SymbolFile/NativePDB/PdbAstBuilder.h | 5 +- .../SymbolFile/NativePDB/SymbolFileNativePDB.cpp | 7 +- llvm/include/llvm/ADT/SmallBitVector.h | 2 +- llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 5 +- .../Transforms/InstCombine/InstCombineAndOrXor.cpp | 22 +- .../AArch64/GlobalISel/arm64-irtranslator.ll | 11 +- llvm/test/CodeGen/AArch64/srem-seteq-optsize.ll | 40 + .../CodeGen/AArch64/srem-seteq-vec-nonsplat.ll | 802 +++++ llvm/test/CodeGen/AArch64/srem-seteq-vec-splat.ll | 157 + llvm/test/CodeGen/AArch64/srem-seteq.ll | 253 ++ .../test/CodeGen/{ARM => Thumb2}/mve-vpt-block.mir | 0 .../CodeGen/{ARM => Thumb2}/mve-vpt-block2.mir | 0 .../CodeGen/{ARM => Thumb2}/mve-vpt-block3.mir | 0 .../CodeGen/{ARM => Thumb2}/mve-vpt-block4.mir | 0 .../CodeGen/{ARM => Thumb2}/mve-vpt-block5.mir | 0 .../CodeGen/{ARM => Thumb2}/mve-vpt-block6.mir | 0 llvm/test/CodeGen/X86/srem-seteq-optsize.ll | 85 + llvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll | 3535 ++++++++++++++++++++ llvm/test/CodeGen/X86/srem-seteq-vec-splat.ll | 586 ++++ llvm/test/CodeGen/X86/srem-seteq.ll | 420 +++ .../InstCombine/2008-12-17-SRemNegConstVec.ll | 7 +- .../InstCombine/2009-06-16-SRemDemandedBits.ll | 15 +- .../InstCombine/2010-01-28-NegativeSRem.ll | 15 +- llvm/test/Transforms/InstCombine/add4.ll | 33 +- llvm/test/Transforms/InstCombine/rem.ll | 85 +- llvm/unittests/ADT/BitVectorTest.cpp | 32 + .../gn/secondary/llvm/tools/llvm-config/BUILD.gn | 2 +- 55 files changed, 6259 insertions(+), 157 deletions(-) create mode 100644 llvm/test/CodeGen/AArch64/srem-seteq-optsize.ll create mode 100644 llvm/test/CodeGen/AArch64/srem-seteq-vec-nonsplat.ll create mode 100644 llvm/test/CodeGen/AArch64/srem-seteq-vec-splat.ll create mode 100644 llvm/test/CodeGen/AArch64/srem-seteq.ll rename llvm/test/CodeGen/{ARM => Thumb2}/mve-vpt-block.mir (100%) rename llvm/test/CodeGen/{ARM => Thumb2}/mve-vpt-block2.mir (100%) rename llvm/test/CodeGen/{ARM => Thumb2}/mve-vpt-block3.mir (100%) rename llvm/test/CodeGen/{ARM => Thumb2}/mve-vpt-block4.mir (100%) rename llvm/test/CodeGen/{ARM => Thumb2}/mve-vpt-block5.mir (100%) rename llvm/test/CodeGen/{ARM => Thumb2}/mve-vpt-block6.mir (100%) create mode 100644 llvm/test/CodeGen/X86/srem-seteq-optsize.ll create mode 100644 llvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll create mode 100644 llvm/test/CodeGen/X86/srem-seteq-vec-splat.ll create mode 100644 llvm/test/CodeGen/X86/srem-seteq.ll