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from 224017fde6a Work around a circular dependency between IR and MC introdu [...] new 9c7e6b20488 [AMDGPU] Constrain the AMDGPU inliner on maximum number of [...] new e9b5b0c8af8 [RISCV] Support Bit-Preserving FP in F/D Extensions
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Summary of changes: lib/Target/AMDGPU/AMDGPUInline.cpp | 16 +- lib/Target/RISCV/RISCVISelLowering.cpp | 5 + lib/Target/RISCV/RISCVISelLowering.h | 2 + test/CodeGen/AMDGPU/inline-maxbb.ll | 33 ++ .../RISCV/float-bit-preserving-dagcombines.ll | 390 +++++++++++++++++++++ 5 files changed, 445 insertions(+), 1 deletion(-) create mode 100644 test/CodeGen/AMDGPU/inline-maxbb.ll create mode 100644 test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll