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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-allyesconfig in repository toolchain/ci/llvm-monorepo.
from 82a6a2bc9d8 [X86] Remove unnecessary code from getMaskNode. adds 72a74f77d75 [RISCV] Add patterns for RV64I SLLW/SRLW/SRAW instructions adds 04a067689a6 [RISCV] Introduce codegen patterns for RV64M-only instructions adds f0944da5f52 [X86] Add ISD node for masked version of CVTPS2PH. adds b9164797fe0 [X86] Remove X86ISD::SELECT as its no longer used by any of [...] adds e44eeed434f [llvm-objcopy] [COFF] Remove pointless Reader/Writer base c [...] adds 5aad1ac7982 Reapply "[DemandedBits] Use SetVector for Worklist" adds ba90f4973fc [X86][AARCH64] Improve ISD::ABS support adds a1476697e91 [X86] Improve vXi64 ISD::ABS codegen with SSE41+ adds 30aa6d86fe5 [ORC][MIPS] Setup t9 register and call function through thi [...] adds 8d198644170 [ORC][MIPS] Fill delay-slot after `jr` instruction adds de3750a175b [NetBSD] Enable additional sanitizer types adds 981a853fa28 [X86] Add more usub.sat vector tests; NFC adds ce18e0f79a4 gn build: Unbreak Windows build adds b94a9b96389 Use getShiftAmountTy for shift amounts. adds 52caf9b64d1 [llvm-objdump] - Change the output for --all-headers. adds b7607e19d8a [analyzer] Fix unused variable warnings in Release builds adds 29b4622cca3 [DAGCombiner] fold insert_subvector of insert_subvector adds e84425d816f [Algorithm] Add make_const_ref corresponding to make_const_ptr adds 8074a00881c [LoopVectorizer] give more advice in remark about failure t [...] adds 998b3b4e79e [ASTDump] Change parameter to StringRef adds 101d9dfd723 Implement TemplateArgument dumping in terms of Visitor adds eddc68a8830 [X86] More aggressive shuffle mask widening in combineExtra [...] adds b7fe7eddc03 [ASTDump] NFC: Move dump of individual Stmts to TextNodeDumper adds 7a8a8481cd0 NFC: Make utility private adds 549d73bbeda Give helper classes/functions local linkage. NFC. adds 875fba9e9cf [X86] Add X86ISD::VMFPROUND to handle the masked case of VC [...] adds c0333ceb38f [X86] Add more ISD nodes to handle masked versions of VCVT( [...]
No new revisions were added by this update.
Summary of changes: clang/include/clang/AST/TemplateArgumentVisitor.h | 99 ++ clang/include/clang/AST/TextNodeDumper.h | 77 +- clang/lib/AST/ASTDumper.cpp | 548 +------ clang/lib/AST/TextNodeDumper.cpp | 524 +++++- clang/lib/Driver/ToolChains/NetBSD.cpp | 4 + clang/lib/StaticAnalyzer/Core/CallEvent.cpp | 7 +- clang/test/Driver/fsanitize.c | 55 +- llvm/include/llvm/ADT/STLExtras.h | 6 + llvm/include/llvm/CodeGen/TargetLowering.h | 8 + .../llvm/ExecutionEngine/Orc/OrcABISupport.h | 4 +- llvm/lib/Analysis/DemandedBits.cpp | 13 +- llvm/lib/AsmParser/LLParser.cpp | 2 +- llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp | 4 +- llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 2 + llvm/lib/CodeGen/GlobalISel/Legalizer.cpp | 2 + llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 8 + llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 4 + .../lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | 19 + llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 21 + llvm/lib/ExecutionEngine/Orc/OrcABISupport.cpp | 19 +- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 67 + llvm/lib/Target/RISCV/RISCVInstrInfo.td | 47 +- llvm/lib/Target/RISCV/RISCVInstrInfoM.td | 31 + llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 1 - llvm/lib/Target/X86/X86ISelLowering.cpp | 74 +- llvm/lib/Target/X86/X86ISelLowering.h | 14 +- llvm/lib/Target/X86/X86InstrAVX512.td | 234 ++- llvm/lib/Target/X86/X86InstrFragmentsSIMD.td | 28 + llvm/lib/Target/X86/X86IntrinsicsInfo.h | 40 +- llvm/lib/Transforms/IPO/HotColdSplitting.cpp | 2 + .../Transforms/Instrumentation/GCOVProfiling.cpp | 2 +- llvm/lib/Transforms/Scalar/LICM.cpp | 2 + llvm/lib/Transforms/Scalar/LoopSimplifyCFG.cpp | 2 + .../Vectorize/LoopVectorizationLegality.cpp | 26 +- llvm/test/CodeGen/AArch64/arm64-vabs.ll | 3 +- llvm/test/CodeGen/RISCV/alu32.ll | 13 +- llvm/test/CodeGen/RISCV/alu64.ll | 17 +- llvm/test/CodeGen/RISCV/div.ll | 251 +++ llvm/test/CodeGen/RISCV/mul.ll | 136 +- llvm/test/CodeGen/RISCV/rem.ll | 38 + .../test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll | 241 +-- .../test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll | 1308 +++++++++++++++ llvm/test/CodeGen/X86/and-load-fold.ll | 3 +- llvm/test/CodeGen/X86/avx512-intrinsics.ll | 2 +- llvm/test/CodeGen/X86/avx512vl-intrinsics.ll | 32 +- llvm/test/CodeGen/X86/combine-abs.ll | 8 +- llvm/test/CodeGen/X86/usub_sat_vec.ll | 1703 ++++++++++++++++++-- llvm/test/CodeGen/X86/vector-reduce-mul-widen.ll | 100 +- llvm/test/CodeGen/X86/vector-reduce-mul.ll | 100 +- llvm/test/CodeGen/X86/viabs.ll | 384 +++-- .../Transforms/LoopVectorize/libcall-remark.ll | 52 + llvm/test/tools/llvm-objdump/all-headers.test | 20 + llvm/tools/llvm-objcopy/COFF/Reader.cpp | 2 - llvm/tools/llvm-objcopy/COFF/Reader.h | 10 +- llvm/tools/llvm-objcopy/COFF/Writer.cpp | 2 - llvm/tools/llvm-objcopy/COFF/Writer.h | 15 +- llvm/tools/llvm-objdump/llvm-objdump.cpp | 10 +- llvm/utils/gn/secondary/llvm/tools/lto/BUILD.gn | 4 +- .../llvm/unittests/ExecutionEngine/MCJIT/BUILD.gn | 2 +- 59 files changed, 5192 insertions(+), 1260 deletions(-) create mode 100644 clang/include/clang/AST/TemplateArgumentVisitor.h create mode 100644 llvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll create mode 100644 llvm/test/Transforms/LoopVectorize/libcall-remark.ll create mode 100644 llvm/test/tools/llvm-objdump/all-headers.test