[Tcwg-commits] [toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-stable-allyesconfig updated (135cf982e8e -> a7972dc04a7)

1 Jul 2019


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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-stable-allyesconfig
in repository toolchain/ci/llvm-project.
from  135cf982e8e Revert "[GDBRemote] Remove code that flushes GDB remote packets"
      adds  bb0b44deaab Clean up MSVC visualization of LLVM pointer types
      adds  fb133b0aabe Various tweaks to MSVC natvis visualizers
      adds  d1728f89878 [X86] Add MOVHPDrm/MOVLPDrm patterns that use VZEXT_LOAD.
      adds  fc233c9108d [X86] Add some additional load folding tests to vec_int_to_ [...]
      adds  4ca81a9b994 [X86] Add a DAG combine to replace vector loads feeding a v [...]
      adds  29fff0797b2 [X86] Improve the type checking fast-isel handling of vecto [...]
      adds  fcda45a9eb8 [X86] Add more load folding tests for vcvt(t)ps2(u)qq showi [...]
      adds  b739b91cd3a [clangd] Make FixIt message be consistent with the clang-ti [...]
      adds  0384a780549 [libcxx] [test] Add void cast to result of compare_exchange [...]
      adds  98722691b0b [ARM] WLS/LE Code Generation
      adds  d4097b4a93a [SimpleLoopUnswitch] Implement handling of prof branch_weig [...]
      adds  9d34f4569b4 [clangd] Show better message when we rename macros.
      adds  d2b6665e339 [DebugInfo] Avoid adding too much indirection to pointer-va [...]
      adds  0f82f64c832 [NFC][InstCombine] Copy test for omit urem when possible fr [...]
      adds  f55818e3a72 [InstCombine] Omit 'urem' where possible
      adds  4f878fe3a7d [NFC][InstCombine] Tests for x - ~(y)  ->  x + y + 1 fold ( [...]
      adds  9cca81344c8 [clangd] Make PreambleStatusCache handle filenames more carefully
      adds  60300c9c7d6 [clangd] Fix unused var from r364735
      adds  d74f2d0a860 [benchmark] Disable CMake get_git_version
      adds  ed13fef4774 [SelectionDAG] Do minnum->minimum at legalization time inst [...]
      adds  0f73709cb71 Remove null checks of results of new expressions
      adds  172fe5dd191 [X86] CombineShuffleWithExtract - updated description comme [...]
      adds  92e78b7bedb [RISCV] Add break; to the last switch case
      adds  881aab4dc3d [clangd] No longer getting template instantiations from hea [...]
      adds  4f0a3772805 Fix TestGdbRemoteLibrariesSvr4Support
      adds  d5c3e34cb7e [NFC][InstCombine] Tests for  ((~x) + y) + 1 -> y - x fold  [...]
      adds  33c8c0ea275 [AMDGPU] Call isLoopExiting for blocks in the loop.
      adds  08c38f77c5f Revert "Implement xfer:libraries-svr4:read packet"
      adds  17c3eafb2e3 [ASTImporter] Propagate error from ImportDeclContext
      adds  77c04c3a577 @skipIfXmlSupportMissing TestRecognizeBreakpoint
      adds  c12dfcf1f56 Don't check the validity of newly contructed data buffers
      adds  3a10810b7ab [mips] Add missing schedinfo for ADJCALLSTACKDOWN, ADJCALLSTACKUP
      adds  c0121bf8741 [mips] Add missing schedinfo for atomic instructions
      adds  ceb9da5bc79 [mips] Add missing schedinfo for MSA and ASE instructions
      adds  fbf67d88de2 GlobalISel: Add DAG compat for G_FCANONICALIZE
      adds  01bb075c1f9 GlobalISel: Add GINodeEquiv for min/max
      adds  5dafcb9b118 AMDGPU/GlobalISel: Use and instead of BFE with inline immediate
      adds  9f992c238ab AMDGPU/GlobalISel: Fix scc->vcc copy handling
      adds  facf69e8449 AMDGPU/GlobalISel: Use vcc reg bank for amdgcn.wqm.vote
      adds  c23149f612d AMDGPU/GlobalISel: RegBankSelect for WWM/WQM
      adds  9f3645869cf [NFC][InstCombine] Improve test coverage for  ((~x) + y) +  [...]
      adds  3b7668ae4bb AMDGPU/GlobalISel: Improve icmp selection coverage.
      adds  89fc8bcdd6d AMDGPU/GlobalISel: Fail on store to 32-bit address space
      adds  b5fc94f3e74 AMDGPU/GlobalISel: Fix RegBankSelect for G_BUILD_VECTOR
      adds  5bf850d52e0 AMDGPU/GlobalISel: Fix RegBankSelect for G_FCANONICALIZE
      adds  1b317685e9b AMDGPU: Convert some places to Register
      adds  511ad50db41 [Hexagon] Rework VLCR algorithm
      adds  1ad4b99d948 [ASTImporter] Mark erroneous nodes in from ctx
      adds  34a0b16e290 [NFC][InstCombine] Better commutative tests for "shift amou [...]
      adds  3f594ed1686 Fix lookup of symbols at the same address with no size vs. size
      adds  4f769361e35 [ASTImporter] Silence unused variable warning in Release bu [...]
      adds  ee6539341bf [UpdateTestChecks][PowerPC] Avoid empty string when scrubbi [...]
      adds  535f39ce521 Revert "[lldb] [Process/NetBSD] Fix constructor after r363707"
      adds  28145735f7b [RISCV] Avoid save-restore target feature warning
      adds  2ba16011c13 Fixup r364512
      adds  2b2ad9342e6 [lldb] [Process/NetBSD] Support reading YMM registers via P [...]
      adds  baf64b65056 [lldb] [Process/NetBSD] Fix segfault when handling watchpoint
      adds  0856721e3a0 [lldb] [Process/NetBSD] Use global enable bits for watchpoints
      adds  4f64ade04cb AMDGPU/GlobalISel: Select src modifiers
      adds  fb99fc7a689 AMDGPU: Fix tests using the default alloca address space
      adds  1daad91af69 AMDGPU/GlobalISel: Tolerate copies with no type set
      adds  2afbfb6b226 [ASTImporter] Mark erroneous nodes in shared st
      adds  6464280eb04 AMDGPU/GlobalISel: Select G_BRCOND for scc conditions
      adds  fdf36729c71 AMDGPU/GlobalISel: Make s16 select legal
      adds  7cfd99ab15d AMDGPU/GFX10: fix scratch resource descriptor
      adds  cda82f0bb6f AMDGPU/GlobalISel: Select G_FRAME_INDEX
      adds  5abf80cdfa3 [Hexagon] Custom-lower UADDO(x, 1) and USUBO(x, 1)
      adds  72b8d41ce81 [InstCombine] Shift amount reassociation in bittest (PR42399)
      adds  04d3d3bbff5 [InstCombine] (Y + ~X) + 1 --> Y - X  fold (PR42459)
      adds  657f8c16c19 Update email address in CODE_OWNERS
      adds  4a9e3f15bbb [ARM] MVE: support QQPRRegClass and QQQQPRRegClass
      adds  2ab25f9ceb1 AMDGPU/GlobalISel: Select G_BRCOND for vcc
      adds  8b2e304bc57 [ARM] Fix MVE_VQxDMLxDH instruction class
      adds  9e9dd30de3a AMDGPU/GlobalISel: Implement select for 32-bit G_ADD
      adds  ba41d3b1fd6 Fix -Wdouble-promotion warnings.
      adds  4603460a395 __threading_support: Remove (void) in favor of ().
      adds  90c57e00015 [docs][llvm-readelf] Expand llvm-readelf documentation
      adds  62d64b0c308 AMDGPU/GlobalISel: RegBankSelect for readlane/readfirstlane
      adds  3c125fe821c Implement LWG2221: 'Formatted output for nullptr_t' Reviewe [...]
      adds  e3e38cce4ab [X86] Add widenSubVector to size in bits helper. NFCI.
      adds  d810ff25888 AMDGPU/GlobalISel: Try to select VOP3 form of add
      adds  e1006259d84 AMDGPU/GlobalISel: Select G_PHI
      adds  0a52e9d026a AMDGPU/GlobalISel: Complete implementation of G_GEP
      adds  a310727830f AMDGPU/GlobalISel: Fail instead of assert when selecting loads
      adds  265059eaf6c AMDGPU/GlobalISel: RegBankSelect for amdgcn.writelane
      adds  8cae7d79b55 Summary: [Clangd] Added hidden command line option -tweaks  [...]
      adds  732149b24eb AArch64/GlobalISel: Fix trying to select invalid MIR
      adds  1094e6a8143 AMDGPU/GlobalISel: RegBankSelect for DS ordered add/swap
      adds  f01fa40a006 [ELF][RISCV] Support PLT, GOT, copy and relative relocations
      adds  ddc57afab9e [ELF][RISCV] Support GD/LD/IE/LE TLS models
      adds  4dc3b2bf95b AMDGPU: Support GDS atomics
      adds  10c911db63e AMDGPU/GFX10: implement ds_ordered_count changes
      adds  6f74f557500 GlobalISel: Implement lower for min/max
      adds  40d1faf38f9 AMDGPU/GlobalISel: Legalize s16 fcmp
      adds  e9345866809 [TSan] Improve handling of stack pointer mangling in {set,l [...]
      adds  b2ea20eedd6 AMDGPU/GlobalISel: RegBankSelect for sendmsg/sendmsghalt
      adds  b600ae37a52 [OPENMP]Fix handling of lambda captures in target regions.
      adds  1023a2eca3f [GlobalISel]: Allow backends to custom legalize Intrinsics
      adds  03ca176ab32 GlobalISel: Verify G_MERGE_VALUES operand sizes
      adds  b7fb723ea38 [TSan] Fix initialized and declared ‘extern’ warning
      adds  e62857786f9 [NFC][InstCombine] Add tests for "shift direction in bittes [...]
      adds  9470bb262b5 AMDGPU/GlobalISel: Fix allowing non-boolean conditions for  [...]
      adds  55d2e6f1c26 [lldb] [lldbsuite] Use a unique class name for TestBacktraceAll
      adds  ef59cb69822 AMDGPU/GlobalISel: Legalize s16 add/sub/mul
      adds  7f8c7209397 AMDGPU/GlobalISel: Add tests for add legalization
      adds  e20030f6121 [X86] Avoid SFB - Fix inconsistent codegen with/without deb [...]
      adds  5a7d5111e58 AMDGPU/GlobalISel: Lower SALU min/max to cmp+select
      adds  4073b33786c AMDGPU/GlobalISel: Handle 16-bit SALU min/max
      adds  e15770aec42 AMDGPU/GlobalISel: Custom lower control flow intrinsics
      adds  e2c86cce3a2 AMDGPU/GlobalISel: Legalize workitem ID intrinsics
      adds  756d81905f6 AMDGPU/GlobalISel: Legalize workgroup ID intrinsics
      adds  9e8e8c60fa1 AMDGPU/GlobalISel: Lower kernarg segment ptr intrinsics
      adds  bae3636f969 AMDGPU/GlobalISel: Handle more input argument intrinsics
      adds  b101c39f587 Fixed two issues in clang-tidy -help.
      adds  5e7815b695d [X86] Correct v4f32->v2i64 cvt(t)ps2(u)qq memory isel patterns
      adds  73dec22c3ef AMDGPU: Revert accidental change to test
      adds  24edf8ef4b5 Implement P0646R1: Erase-Like Algorithms Should Return size [...]
      adds  c9f14f29f5c GlobalISel: Try to widen merges with other merges
      adds  d1523f7a8c2 Ensure bitset's string constructor doesn't poison the overl [...]
      adds  8b7a0baa20c Testing commit access through minor formatting change
      adds  975120a21b4 [NFC][InstCombine] More commutative tests for "shift direct [...]
      adds  d7fcee62f11 [Core] Generalize ValueObject::IsRuntimeSupportValue
       new  a7972dc04a7 Revert [SLP] Look-ahead operand reordering heuristic.
The 1 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails.  The revisions
listed as "adds" were already present in the repository and have only
been added to this reference.
Summary of changes:
 .../clang-tidy/tool/ClangTidyMain.cpp              |    4 +-
 clang-tools-extra/clangd/ClangdServer.cpp          |    3 +-
 clang-tools-extra/clangd/ClangdServer.h            |    7 +-
 clang-tools-extra/clangd/ClangdUnit.cpp            |    3 +-
 clang-tools-extra/clangd/Diagnostics.cpp           |    2 +
 clang-tools-extra/clangd/FS.cpp                    |   19 +-
 clang-tools-extra/clangd/SourceCode.cpp            |   27 +
 clang-tools-extra/clangd/SourceCode.h              |    8 +
 clang-tools-extra/clangd/XRefs.cpp                 |   76 +-
 clang-tools-extra/clangd/refactor/Rename.cpp       |   43 +-
 .../clangd/test/fixits-duplication.test            |    2 +-
 clang-tools-extra/clangd/tool/ClangdMain.cpp       |   11 +
 .../clangd/unittests/ClangdUnitTests.cpp           |   20 +
 .../clangd/unittests/DiagnosticsTests.cpp          |   22 +-
 clang-tools-extra/clangd/unittests/FSTests.cpp     |   12 +-
 clang-tools-extra/clangd/unittests/RenameTests.cpp |    7 +
 .../clangd/unittests/SourceCodeTests.cpp           |   17 +
 clang-tools-extra/docs/clang-tidy/index.rst        |  210 +--
 clang/include/clang/AST/ASTImporter.h              |  144 +-
 clang/include/clang/AST/ASTImporterSharedState.h   |   80 +
 clang/include/clang/CrossTU/CrossTranslationUnit.h |    6 +-
 clang/include/clang/Sema/Sema.h                    |    4 +
 clang/lib/AST/ASTImporter.cpp                      |  112 +-
 clang/lib/CrossTU/CrossTranslationUnit.cpp         |   10 +-
 clang/lib/Driver/ToolChains/Arch/RISCV.cpp         |    8 +-
 clang/lib/Frontend/ASTMerge.cpp                    |    6 +-
 clang/lib/Sema/SemaExpr.cpp                        |    2 +
 clang/lib/Sema/SemaOpenMP.cpp                      |   97 +-
 clang/lib/Tooling/CommonOptionsParser.cpp          |    2 +-
 clang/test/Driver/riscv-features.c                 |    8 +-
 clang/test/OpenMP/nvptx_lambda_capturing.cpp       |   10 +-
 clang/unittests/AST/ASTImporterFixtures.cpp        |   45 +-
 clang/unittests/AST/ASTImporterFixtures.h          |   28 +-
 clang/unittests/AST/ASTImporterTest.cpp            |  367 +++-
 clang/utils/ClangVisualizers/clang.natvis          |   54 +-
 compiler-rt/lib/tsan/rtl/tsan_interceptors.cc      |   11 +-
 compiler-rt/lib/tsan/rtl/tsan_platform_linux.cc    |    7 +-
 compiler-rt/lib/tsan/rtl/tsan_rtl.h                |    1 -
 libcxx/include/__threading_support                 |    4 +-
 libcxx/include/bitset                              |    4 +-
 libcxx/include/forward_list                        |   43 +-
 libcxx/include/limits                              |    2 +-
 libcxx/include/list                                |   34 +-
 libcxx/include/ostream                             |    5 +
 libcxx/include/type_traits                         |    4 +
 libcxx/include/utility                             |    4 +-
 .../atomics.general/replace_failure_order.pass.cpp |    8 +-
 .../forwardlist/forwardlist.ops/remove.pass.cpp    |   24 +-
 .../forwardlist/forwardlist.ops/remove_if.pass.cpp |   20 +-
 .../forwardlist/forwardlist.ops/unique.pass.cpp    |   20 +-
 .../sequences/list/list.ops/remove.pass.cpp        |    8 +-
 .../sequences/list/list.ops/remove_if.pass.cpp     |    6 +-
 .../sequences/list/list.ops/unique.pass.cpp        |    4 +-
 .../ostream.inserters/streambuf.pass.cpp           |    7 +
 .../bitset.cons/string_ctor.pass.cpp               |   13 +
 libcxx/www/cxx1z_status.html                       |    2 +-
 lld/ELF/Arch/RISCV.cpp                             |  154 +-
 lld/ELF/InputSection.cpp                           |    5 +-
 lld/ELF/Relocations.cpp                            |    2 +-
 lld/test/ELF/riscv-plt.s                           |  103 ++
 lld/test/ELF/riscv-reloc-64-pic.s                  |   10 +
 lld/test/ELF/riscv-reloc-copy.s                    |   23 +
 lld/test/ELF/riscv-reloc-got.s                     |   65 +
 lld/test/ELF/riscv-tls-gd.s                        |  124 ++
 lld/test/ELF/riscv-tls-ie.s                        |   82 +
 lld/test/ELF/riscv-tls-ld.s                        |   90 +
 lld/test/ELF/riscv-tls-le.s                        |   41 +
 lld/test/ELF/riscv32-reloc-32-pic.s                |   23 +
 lld/test/ELF/riscv64-reloc-64-pic.s                |   23 +
 .../lldb/Host/common/NativeProcessProtocol.h       |   14 -
 lldb/include/lldb/Target/CPPLanguageRuntime.h      |    2 +-
 lldb/include/lldb/Target/LanguageRuntime.h         |    6 +-
 lldb/include/lldb/Target/ObjCLanguageRuntime.h     |    3 +-
 lldb/lit/SymbolFile/Inputs/sizeless-symbol.s       |    8 +
 lldb/lit/SymbolFile/sizeless-symbol.test           |   14 +
 .../gdb_remote_client/TestRecognizeBreakpoint.py   |    1 +
 .../thread/backtrace_all/TestBacktraceAll.py       |    2 +-
 .../hello_watchlocation/TestWatchLocation.py       |    1 -
 .../hello_watchpoint/TestMyFirstWatchpoint.py      |    1 -
 .../watchpoint/multiple_hits/TestMultipleHits.py   |    1 -
 .../TestWatchpointMultipleThreads.py               |    2 -
 .../step_over_watchpoint/TestStepOverWatchpoint.py |    1 -
 .../watchpoint_commands/TestWatchpointCommands.py  |    4 -
 .../command/TestWatchpointCommandLLDB.py           |    2 -
 .../command/TestWatchpointCommandPython.py         |    2 -
 .../condition/TestWatchpointConditionCmd.py        |    1 -
 .../watchpoint_disable/TestWatchpointDisable.py    |    1 -
 .../TestWatchLocationWithWatchSet.py               |    1 -
 .../watchpoint_size/TestWatchpointSizes.py         |    3 -
 .../test/tools/lldb-server/gdbremote_testcase.py   |   29 +-
 .../test/tools/lldb-server/libraries-svr4/Makefile |   17 -
 .../TestGdbRemoteLibrariesSvr4Support.py           |  130 --
 .../test/tools/lldb-server/libraries-svr4/main.cpp |   15 -
 .../tools/lldb-server/libraries-svr4/svr4lib_a.cpp |    9 -
 .../tools/lldb-server/libraries-svr4/svr4lib_a.mk  |    9 -
 .../lldb-server/libraries-svr4/svr4lib_b_quote.cpp |    9 -
 .../lldb-server/libraries-svr4/svr4lib_b_quote.mk  |    9 -
 lldb/source/Core/ValueObject.cpp                   |   32 +-
 .../Plugins/ObjectFile/JIT/ObjectFileJIT.cpp       |   14 +-
 .../RegisterContextPOSIXProcessMonitor_arm.cpp     |    2 +-
 .../RegisterContextPOSIXProcessMonitor_arm64.cpp   |    2 +-
 .../RegisterContextPOSIXProcessMonitor_mips64.cpp  |    2 +-
 .../RegisterContextPOSIXProcessMonitor_powerpc.cpp |    2 +-
 .../RegisterContextPOSIXProcessMonitor_x86.cpp     |    2 +-
 .../Plugins/Process/Linux/NativeProcessLinux.cpp   |    2 +-
 .../Linux/NativeRegisterContextLinux_arm.cpp       |   11 -
 .../Linux/NativeRegisterContextLinux_arm64.cpp     |   11 -
 .../Linux/NativeRegisterContextLinux_mips64.cpp    |   14 -
 .../Linux/NativeRegisterContextLinux_ppc64le.cpp   |   11 -
 .../Linux/NativeRegisterContextLinux_s390x.cpp     |   14 -
 .../Plugins/Process/NetBSD/NativeProcessNetBSD.cpp |   33 +-
 .../Plugins/Process/NetBSD/NativeProcessNetBSD.h   |    4 +-
 .../NetBSD/NativeRegisterContextNetBSD_x86_64.cpp  |  107 +-
 .../NetBSD/NativeRegisterContextNetBSD_x86_64.h    |   10 +-
 .../Plugins/Process/POSIX/NativeProcessELF.cpp     |   69 -
 .../Plugins/Process/POSIX/NativeProcessELF.h       |    7 -
 .../Utility/RegisterContextDarwin_arm64.cpp        |    4 +-
 .../Process/Utility/RegisterContextDarwin_i386.cpp |    3 +-
 .../Utility/RegisterContextDarwin_x86_64.cpp       |    3 +-
 .../GDBRemoteCommunicationServerCommon.cpp         |    1 -
 .../GDBRemoteCommunicationServerLLGS.cpp           |   43 -
 .../gdb-remote/GDBRemoteCommunicationServerLLGS.h  |    2 -
 .../SymbolFile/DWARF/DWARFASTParserClang.cpp       |    3 +-
 lldb/source/Symbol/Function.cpp                    |    8 +-
 lldb/source/Symbol/Symtab.cpp                      |   10 +-
 lldb/source/Target/CPPLanguageRuntime.cpp          |   16 +-
 lldb/source/Target/ObjCLanguageRuntime.cpp         |   13 -
 llvm/CODE_OWNERS.TXT                               |    2 +-
 .../{llvm-readobj.rst => llvm-readelf.rst}         |  231 +--
 llvm/docs/CommandGuide/llvm-readobj.rst            |   24 +
 .../llvm/CodeGen/GlobalISel/LegalizerHelper.h      |    1 +
 .../llvm/CodeGen/GlobalISel/LegalizerInfo.h        |    5 +
 llvm/include/llvm/IR/DebugInfoMetadata.h           |    4 +
 llvm/include/llvm/IR/IntrinsicsAMDGPU.td           |    2 +
 .../llvm/Target/GlobalISel/SelectionDAGCompat.td   |    5 +
 llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp      |    5 +-
 llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp       |   22 +-
 llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp    |   70 +-
 llvm/lib/CodeGen/GlobalISel/LegalizerInfo.cpp      |    6 +
 llvm/lib/CodeGen/HardwareLoops.cpp                 |    1 +
 llvm/lib/CodeGen/MachineVerifier.cpp               |   10 +
 llvm/lib/CodeGen/PrologEpilogInserter.cpp          |   13 +-
 .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp   |   22 +-
 llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp   |   11 +
 llvm/lib/IR/DebugInfoMetadata.cpp                  |   21 +
 .../Target/AArch64/AArch64InstructionSelector.cpp  |   33 +-
 llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h   |   15 +-
 llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp      |  161 +-
 llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp      |   17 +-
 .../Target/AMDGPU/AMDGPUInstructionSelector.cpp    |  441 +++--
 llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h |   15 +-
 llvm/lib/Target/AMDGPU/AMDGPUInstructions.td       |   21 +
 llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp     |  244 ++-
 llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h       |   18 +
 llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp  |  361 +++-
 llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h    |    7 +
 .../Target/AMDGPU/AMDGPUTargetTransformInfo.cpp    |   11 +-
 llvm/lib/Target/AMDGPU/DSInstructions.td           |   88 +-
 llvm/lib/Target/AMDGPU/SIISelLowering.cpp          |   29 +-
 llvm/lib/Target/AMDGPU/SIInstrInfo.cpp             |    4 +-
 llvm/lib/Target/AMDGPU/SIInstrInfo.td              |    2 +
 llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp   |    7 +-
 llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h     |    9 +-
 llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp          |    4 +-
 llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp            |   10 +
 llvm/lib/Target/ARM/ARMISelLowering.cpp            |   47 +-
 llvm/lib/Target/ARM/ARMISelLowering.h              |    2 +
 llvm/lib/Target/ARM/ARMInstrInfo.td                |    8 +
 llvm/lib/Target/ARM/ARMInstrMVE.td                 |   15 +-
 llvm/lib/Target/ARM/ARMInstrThumb2.td              |   10 +-
 llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp        |  116 +-
 llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp     |    2 +
 llvm/lib/Target/Hexagon/HexagonISelLowering.cpp    |   43 +-
 llvm/lib/Target/Hexagon/HexagonISelLowering.h      |    1 +
 .../Hexagon/HexagonVectorLoopCarriedReuse.cpp      |  220 ++-
 llvm/lib/Target/Mips/MipsDSPInstrInfo.td           |    1 +
 llvm/lib/Target/Mips/MipsInstrInfo.td              |   11 +-
 llvm/lib/Target/Mips/MipsMSAInstrInfo.td           |    7 +-
 llvm/lib/Target/Mips/MipsScheduleP5600.td          |   22 +
 llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp |    1 +
 .../Target/X86/X86AvoidStoreForwardingBlocks.cpp   |    4 +
 llvm/lib/Target/X86/X86FastISel.cpp                |   21 +-
 llvm/lib/Target/X86/X86ISelLowering.cpp            |   95 +-
 llvm/lib/Target/X86/X86InstrAVX512.td              |   78 +-
 llvm/lib/Target/X86/X86InstrSSE.td                 |   12 +
 .../Transforms/InstCombine/InstCombineAddSub.cpp   |    5 +-
 .../Transforms/InstCombine/InstCombineCompares.cpp |   84 +-
 llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp  |   56 +-
 llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp    |  282 +--
 .../CodeGen/AMDGPU/GlobalISel/inst-select-add.mir  |   56 +
 .../inst-select-amdgcn.kernarg.segment.ptr.mir     |   19 -
 .../AMDGPU/GlobalISel/inst-select-anyext.mir       |   36 +
 .../CodeGen/AMDGPU/GlobalISel/inst-select-br.mir   |   21 +
 .../AMDGPU/GlobalISel/inst-select-brcond.mir       |  198 +++
 .../CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir |  170 +-
 .../GlobalISel/inst-select-fcanonicalize.mir       |  164 ++
 .../CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir |  190 +-
 .../AMDGPU/GlobalISel/inst-select-frame-index.mir  |   38 +
 .../CodeGen/AMDGPU/GlobalISel/inst-select-gep.mir  |  354 ++++
 .../AMDGPU/GlobalISel/inst-select-icmp.s64.mir     |  595 +++++++
 .../AMDGPU/GlobalISel/inst-select-implicit-def.mir |    6 +-
 .../AMDGPU/GlobalISel/inst-select-load-smrd.mir    |   44 +-
 .../AMDGPU/GlobalISel/inst-select-phi-invalid.mir  |   31 +
 .../CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir  |  385 ++++
 .../AMDGPU/GlobalISel/inst-select-select.mir       |  176 ++
 .../CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir |   39 +
 .../CodeGen/AMDGPU/GlobalISel/inst-select-smax.mir |   83 +
 .../CodeGen/AMDGPU/GlobalISel/inst-select-smin.mir |   83 +
 .../CodeGen/AMDGPU/GlobalISel/inst-select-umax.mir |   83 +
 .../CodeGen/AMDGPU/GlobalISel/inst-select-umin.mir |   83 +
 .../CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir |   48 +-
 .../irtranslator-amdgpu_kernel-system-sgprs.ll     |  118 +-
 .../AMDGPU/GlobalISel/irtranslator-amdgpu_ps.ll    |    2 +-
 .../AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll    |   18 +-
 .../GlobalISel/irtranslator-fast-math-flags.ll     |    2 +-
 .../CodeGen/AMDGPU/GlobalISel/legalize-add.mir     |  233 ++-
 .../GlobalISel/legalize-amdgcn.if-invalid.mir      |   73 +
 .../CodeGen/AMDGPU/GlobalISel/legalize-brcond.mir  |  126 +-
 .../CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir    |  323 +++-
 .../CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir    |   20 +-
 .../AMDGPU/GlobalISel/legalize-merge-values.mir    |  345 +++-
 .../CodeGen/AMDGPU/GlobalISel/legalize-mul.mir     |  285 ++-
 .../CodeGen/AMDGPU/GlobalISel/legalize-select.mir  |  110 +-
 .../CodeGen/AMDGPU/GlobalISel/legalize-sub.mir     |  146 +-
 .../AMDGPU/GlobalISel/llvm.amdgcn.dispatch.id.ll   |   19 +
 .../AMDGPU/GlobalISel/llvm.amdgcn.dispatch.ptr.ll  |   18 +
 .../GlobalISel/llvm.amdgcn.implicit.buffer.ptr.ll  |   17 +
 .../GlobalISel/llvm.amdgcn.kernarg.segment.ptr.ll  |  125 ++
 .../AMDGPU/GlobalISel/llvm.amdgcn.queue.ptr.ll     |   18 +
 .../AMDGPU/GlobalISel/llvm.amdgcn.workgroup.id.ll  |  106 ++
 .../AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll   |   92 +
 .../regbankselect-amdgcn.ds.ordered.add.mir        |   71 +
 .../regbankselect-amdgcn.ds.ordered.swap.mir       |   71 +
 .../regbankselect-amdgcn.readfirstlane.mir         |   32 +
 .../GlobalISel/regbankselect-amdgcn.readlane.mir   |   71 +
 .../GlobalISel/regbankselect-amdgcn.s.sendmsg.mir  |   32 +
 .../regbankselect-amdgcn.s.sendmsghalt.mir         |   32 +
 .../AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir |   31 +
 ...-vote.mir => regbankselect-amdgcn.wqm.vote.mir} |   10 +-
 .../GlobalISel/regbankselect-amdgcn.writelane.mir  |   98 ++
 .../AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir |   31 +
 .../GlobalISel/regbankselect-build-vector.mir      |   69 +
 .../GlobalISel/regbankselect-fcanonicalize.mir     |   35 +
 .../AMDGPU/GlobalISel/regbankselect-phi.mir        | 1849 +++++++++++++-------
 .../AMDGPU/GlobalISel/regbankselect-select.mir     | 1451 ++++++++++-----
 .../AMDGPU/GlobalISel/regbankselect-smax.mir       |  170 +-
 .../AMDGPU/GlobalISel/regbankselect-smin.mir       |  170 +-
 .../AMDGPU/GlobalISel/regbankselect-umax.mir       |  170 +-
 .../AMDGPU/GlobalISel/regbankselect-umin.mir       |  170 +-
 llvm/test/CodeGen/AMDGPU/gds-atomic.ll             |  128 ++
 .../AMDGPU/llvm.amdgcn.ds.ordered.add.gfx10.ll     |   23 +
 llvm/test/CodeGen/AMDGPU/loop-idiom.ll             |   13 +-
 llvm/test/CodeGen/AMDGPU/scratch-simple.ll         |   65 +-
 llvm/test/CodeGen/AMDGPU/unroll.ll                 |   17 +-
 ...exagon_vector_loop_carried_reuse_commutative.ll |   82 +
 llvm/test/CodeGen/Hexagon/isel-uaddo-1.ll          |   37 +
 llvm/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll   |  178 +-
 .../Thumb2/LowOverheadLoops}/cond-mov.mir          |    0
 .../CodeGen/Thumb2/LowOverheadLoops/loop-guards.ll |  213 +++
 .../Thumb2/LowOverheadLoops}/massive.mir           |    0
 .../LowOverheadLoops}/multiblock-massive.mir       |    0
 .../Thumb2/LowOverheadLoops}/revert-after-call.mir |    0
 .../LowOverheadLoops}/revert-after-spill.mir       |    0
 .../Thumb2/LowOverheadLoops/revert-while.mir       |  130 ++
 .../Thumb2/LowOverheadLoops}/size-limit.mir        |    0
 .../Thumb2/LowOverheadLoops}/switch.mir            |    0
 .../test/CodeGen/Thumb2/LowOverheadLoops/while.mir |  131 ++
 llvm/test/CodeGen/WebAssembly/f32.ll               |   18 +
 llvm/test/CodeGen/WebAssembly/simd-arith.ll        |   22 +
 llvm/test/CodeGen/X86/avoid-sfb-g-no-change2.mir   |  198 +++
 llvm/test/CodeGen/X86/avoid-sfb-g-no-change3.mir   |  223 +++
 llvm/test/CodeGen/X86/avx512dqvl-intrinsics.ll     |  655 ++++++-
 .../CodeGen/X86/merge-consecutive-loads-128.ll     |    3 +-
 llvm/test/CodeGen/X86/pr42452.ll                   |   37 +
 llvm/test/CodeGen/X86/vec_fp_to_int-widen.ll       |  150 ++
 llvm/test/CodeGen/X86/vec_fp_to_int.ll             |  150 ++
 llvm/test/CodeGen/X86/vec_int_to_fp-widen.ll       |  794 +++++++--
 llvm/test/CodeGen/X86/vec_int_to_fp.ll             |  472 +++--
 .../MIR/X86/prolog-epilog-indirection.mir          |  130 ++
 llvm/test/MachineVerifier/test_g_merge_values.mir  |   28 +
 llvm/test/Transforms/HardwareLoops/ARM/do-rem.ll   |   32 +-
 .../Transforms/HardwareLoops/ARM/fp-emulation.ll   |   23 +-
 .../test/Transforms/HardwareLoops/ARM/simple-do.ll |   42 +-
 .../test/Transforms/HardwareLoops/ARM/structure.ll |   95 +-
 llvm/test/Transforms/InstCombine/add.ll            |   10 +-
 ...ld-inc-of-add-of-not-x-and-y-to-sub-x-from-y.ll |  213 +++
 .../InstCombine/fold-sub-of-not-to-inc-of-add.ll   |   94 +
 ...ower-of-two-or-zero-when-comparing-with-zero.ll |  166 ++
 .../shift-amount-reassociation-in-bittest.ll       |  318 ++--
 .../InstCombine/shift-direction-in-bit-test.ll     |  279 +++
 .../test/Transforms/SLPVectorizer/X86/lookahead.ll |  134 +-
 .../SimpleLoopUnswitch/basictest-profmd.ll         |   34 +
 .../SimpleLoopUnswitch/trivial-unswitch-profmd.ll  |  228 +++
 .../CodeGen/GlobalISel/LegalizerHelperTest.cpp     |   78 +
 llvm/utils/LLVMVisualizers/llvm.natvis             |   19 +-
 llvm/utils/UpdateTestChecks/asm.py                 |    4 +-
 llvm/utils/benchmark/CMakeLists.txt                |    7 +-
 llvm/utils/benchmark/README.LLVM                   |    2 +
 298 files changed, 17615 insertions(+), 4020 deletions(-)
 create mode 100644 clang/include/clang/AST/ASTImporterSharedState.h
 create mode 100644 lld/test/ELF/riscv-plt.s
 create mode 100644 lld/test/ELF/riscv-reloc-64-pic.s
 create mode 100644 lld/test/ELF/riscv-reloc-copy.s
 create mode 100644 lld/test/ELF/riscv-reloc-got.s
 create mode 100644 lld/test/ELF/riscv-tls-gd.s
 create mode 100644 lld/test/ELF/riscv-tls-ie.s
 create mode 100644 lld/test/ELF/riscv-tls-ld.s
 create mode 100644 lld/test/ELF/riscv-tls-le.s
 create mode 100644 lld/test/ELF/riscv32-reloc-32-pic.s
 create mode 100644 lld/test/ELF/riscv64-reloc-64-pic.s
 create mode 100644 lldb/lit/SymbolFile/Inputs/sizeless-symbol.s
 create mode 100644 lldb/lit/SymbolFile/sizeless-symbol.test
 delete mode 100644 lldb/packages/Python/lldbsuite/test/tools/lldb-server/libraries [...]
 delete mode 100644 lldb/packages/Python/lldbsuite/test/tools/lldb-server/libraries [...]
 delete mode 100644 lldb/packages/Python/lldbsuite/test/tools/lldb-server/libraries [...]
 delete mode 100644 lldb/packages/Python/lldbsuite/test/tools/lldb-server/libraries [...]
 delete mode 100644 lldb/packages/Python/lldbsuite/test/tools/lldb-server/libraries [...]
 delete mode 100644 lldb/packages/Python/lldbsuite/test/tools/lldb-server/libraries [...]
 delete mode 100644 lldb/packages/Python/lldbsuite/test/tools/lldb-server/libraries [...]
 copy llvm/docs/CommandGuide/{llvm-readobj.rst => llvm-readelf.rst} (57%)
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir
 delete mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.kernarg. [...]
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-br.mir
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-brcond.mir
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcanonicalize.mir
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-frame-index.mir
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-gep.mir
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.s64.mir
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-phi-invalid.mir
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-select.mir
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smax.mir
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smin.mir
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umax.mir
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umin.mir
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.if-invalid.mir
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.dispatch.id.ll
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.dispatch.ptr.ll
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.implicit.buffer.ptr.ll
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.kernarg.segment.ptr.ll
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.queue.ptr.ll
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workgroup.id.ll
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ord [...]
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ord [...]
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readfi [...]
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readlane.mir
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsg.mir
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.send [...]
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir
 rename llvm/test/CodeGen/AMDGPU/GlobalISel/{regbankselect-amdgcn-wqm-vote.mir => r [...]
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.writelane.mir
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector.mir
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcanonicalize.mir
 create mode 100644 llvm/test/CodeGen/AMDGPU/gds-atomic.ll
 create mode 100644 llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add.gfx10.ll
 create mode 100644 llvm/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse_com [...]
 create mode 100644 llvm/test/CodeGen/Hexagon/isel-uaddo-1.ll
 rename llvm/test/{Transforms/HardwareLoops/ARM => CodeGen/Thumb2/LowOverheadLoops} [...]
 create mode 100644 llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-guards.ll
 rename llvm/test/{Transforms/HardwareLoops/ARM => CodeGen/Thumb2/LowOverheadLoops} [...]
 rename llvm/test/{Transforms/HardwareLoops/ARM => CodeGen/Thumb2/LowOverheadLoops} [...]
 rename llvm/test/{Transforms/HardwareLoops/ARM => CodeGen/Thumb2/LowOverheadLoops} [...]
 rename llvm/test/{Transforms/HardwareLoops/ARM => CodeGen/Thumb2/LowOverheadLoops} [...]
 create mode 100644 llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir
 rename llvm/test/{Transforms/HardwareLoops/ARM => CodeGen/Thumb2/LowOverheadLoops} [...]
 rename llvm/test/{Transforms/HardwareLoops/ARM => CodeGen/Thumb2/LowOverheadLoops} [...]
 create mode 100644 llvm/test/CodeGen/Thumb2/LowOverheadLoops/while.mir
 create mode 100644 llvm/test/CodeGen/X86/avoid-sfb-g-no-change2.mir
 create mode 100644 llvm/test/CodeGen/X86/avoid-sfb-g-no-change3.mir
 create mode 100644 llvm/test/CodeGen/X86/pr42452.ll
 create mode 100644 llvm/test/DebugInfo/MIR/X86/prolog-epilog-indirection.mir
 create mode 100644 llvm/test/MachineVerifier/test_g_merge_values.mir
 create mode 100644 llvm/test/Transforms/InstCombine/fold-inc-of-add-of-not-x-and-y [...]
 create mode 100644 llvm/test/Transforms/InstCombine/fold-sub-of-not-to-inc-of-add.ll
 create mode 100644 llvm/test/Transforms/InstCombine/omit-urem-of-power-of-two-or-z [...]
 create mode 100644 llvm/test/Transforms/InstCombine/shift-direction-in-bit-test.ll
 create mode 100644 llvm/test/Transforms/SimpleLoopUnswitch/basictest-profmd.ll
 create mode 100644 llvm/test/Transforms/SimpleLoopUnswitch/trivial-unswitch-profmd.ll
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[Tcwg-commits] [toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-stable-allyesconfig updated (135cf982e8e -> a7972dc04a7)