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from b398d8e1fa5 [X86] Fix some isel patterns that used aligned vector load [...] new 76ea6aab07b [AArch64] Fix UB about shift amount exceeds data bit-width
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Summary of changes: lib/Target/AArch64/AArch64ISelDAGToDAG.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)