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from 9882b81410f RISC-V: Make SHA-256, SM3 and SM4 builtins operate on uint32_t new 86451305d8b RISC-V: Expand VLS mode to scalar mode move[PR111391]
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Summary of changes: gcc/config/riscv/autovec.md | 2 +- gcc/config/riscv/riscv-vsetvl.cc | 4 +- gcc/config/riscv/riscv.cc | 64 ++++++++++++++++++++++ .../gcc.target/riscv/rvv/autovec/partial/slp-9.c | 1 - .../gcc.target/riscv/rvv/autovec/pr111391-1.c | 28 ++++++++++ .../gcc.target/riscv/rvv/autovec/pr111391-2.c | 10 ++++ 6 files changed, 106 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111391-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111391-2.c