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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-allnoconfig in repository toolchain/ci/llvm-project.
from b4e06328fc2 [lldb] Fix buildbot build fail caused by r366645 adds 8fabdfe9fcd [InstCombine] Don't use AddOne/SubOne to see if two APInts [...] adds 1d149d08d3a [InstCombine] Remove insertRangeTest code that handles the [...] adds fe1b8a09113 [NativePDB] Make GetOrCreateDeclForUid return an lldb CompilerDecl adds 8a431874e99 [NFC][InstCombine] Add a few extra srem-by-power-of-two tes [...] adds ca9dfdfaeca [lldb] Fix crash when looking up type coming from the Clang [...] adds c38899fc26e [ARM] Move MVE VPT block tests into the Thumb2 directory. NFC adds d7504a1569d [GISel]: Attach missing range metadata while translating G_LOADs adds 630be14ac64 [SmallBitVector] Fix bug in find_next_unset for small types [...] adds e6cd20ba534 [InstCombine] Update comment I missed in r366649. NFC adds 73d641a23c2 [PowerPC][NFC] Regenerate test using script adds 86fa3270ef6 [X86] SimplifyDemandedVectorEltsForTargetNode - Move SUBV_B [...] adds 3d68adebc57 [PowerPC][NFC] Precomit test case for upcoming patch
No new revisions were added by this update.
Summary of changes: .../test/lang/objc/modules/TestObjCModules.py | 4 + .../Clang/ClangModulesDeclVendor.cpp | 12 +- .../Plugins/SymbolFile/NativePDB/PdbAstBuilder.cpp | 16 +- .../Plugins/SymbolFile/NativePDB/PdbAstBuilder.h | 5 +- .../SymbolFile/NativePDB/SymbolFileNativePDB.cpp | 7 +- llvm/include/llvm/ADT/SmallBitVector.h | 2 +- llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 5 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 32 ++-- .../Transforms/InstCombine/InstCombineAndOrXor.cpp | 22 +-- .../AArch64/GlobalISel/arm64-irtranslator.ll | 11 +- llvm/test/CodeGen/PowerPC/dform-adjust.ll | 125 ++++++++++++++ llvm/test/CodeGen/PowerPC/pre-inc-disable.ll | 189 ++++++++++++++++++--- .../test/CodeGen/{ARM => Thumb2}/mve-vpt-block.mir | 0 .../CodeGen/{ARM => Thumb2}/mve-vpt-block2.mir | 0 .../CodeGen/{ARM => Thumb2}/mve-vpt-block3.mir | 0 .../CodeGen/{ARM => Thumb2}/mve-vpt-block4.mir | 0 .../CodeGen/{ARM => Thumb2}/mve-vpt-block5.mir | 0 .../CodeGen/{ARM => Thumb2}/mve-vpt-block6.mir | 0 llvm/test/Transforms/InstCombine/rem.ll | 37 ++++ llvm/unittests/ADT/BitVectorTest.cpp | 32 ++++ 20 files changed, 424 insertions(+), 75 deletions(-) create mode 100644 llvm/test/CodeGen/PowerPC/dform-adjust.ll rename llvm/test/CodeGen/{ARM => Thumb2}/mve-vpt-block.mir (100%) rename llvm/test/CodeGen/{ARM => Thumb2}/mve-vpt-block2.mir (100%) rename llvm/test/CodeGen/{ARM => Thumb2}/mve-vpt-block3.mir (100%) rename llvm/test/CodeGen/{ARM => Thumb2}/mve-vpt-block4.mir (100%) rename llvm/test/CodeGen/{ARM => Thumb2}/mve-vpt-block5.mir (100%) rename llvm/test/CodeGen/{ARM => Thumb2}/mve-vpt-block6.mir (100%)