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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-defconfig in repository toolchain/ci/llvm-project.
from 3b70ee27a50 [LoopExtractor] Convert LoopExtractor from LoopPass to ModulePass adds 644d56b432b [X86] Recognise ROTLI/ROTRI rotations as faux shuffles adds 3ec6de07e91 Fix signed/unsigned warning. adds 420a5180685 [lldb] [testsuite] TestGdbRemoteLibrariesSvr4Support: Fix s [...] adds 0ea4d18a288 [LLDB] [doc] Update the current status of pkgsrc (NetBSD) building adds 5a285f207e1 [LLDB] [doc] Remove note about libpanel(3) and NetBSD adds 8b37e1e5ac0 [lldb] [doc] Testing: Fix typos adds 74857b4260e [lldb] [doc] Status: Debugserver (remote debugging) is OK now adds a17f03bd939 [VectorCombine] new IR transform pass for partial vector ops adds 628462e30a7 [gn build] Port a17f03bd939 adds 273f638384d [LLDB] [doc] Document NetBSD status and sort OSs alphabetically adds 9d223a0106d [lldb] [doc] Status: Linux: Update the paragraph adds 29621b25346 [X86] Rename matchShuffleAsRotate - matchShuffleAsByteRotat [...] adds 22780731255 [X86][SSE] Add more tests showing failure to lower shuffles [...] adds 0ae119f8356 [X86][XOP] Add XOP target to vXi16/vXi8 shuffle tests adds 4b23a2e8e97 libclc: Move rsqrt implementation to a .cl file adds 85e2fa44c64 libclc/r600: Use target specific builtins to implement rsqr [...] adds dbcc1392b38 [X86] Remove isel patterns that include a vselect/X86select [...] adds dd262222b40 [X86] Use MVT::i32 for the type of a MOV32r0 created in X86 [...] adds e82e17d4d4c [X86] Add lowerShuffleAsBitRotate (PR44379) adds e1cbfecdb86 [X86] Add flag result VT to a MOV32r0 created in X86DAGToDA [...] adds 656d66f5fc5 [X86] Use custom isel for (X86sbb_flag 0, 0) so we can use [...] adds 29e646fe655 [X86] combineConcatVectorOps - combine VROTLI/VROTRI ops adds 6e1770821fb AMDGPU: Fix SI_IF lowering when the save exec reg has termi [...] adds 00115d767f3 AMDGPU: Remove dead kill handling adds f4a38c114e1 AMDGPU/GlobalISel: Look through casts when legalizing vecto [...] adds 2126c70e3a6 AMDGPU/GlobalISel: Don't mis-select vector index on a constant adds 6135f5eda48 GlobalISel: Fix narrowing of G_CTLZ/G_CTTZ adds c437f6c6873 AMDGPU/GlobalISel: Split 64-bit G_CTPOP in RegBankSelect adds 312a9d1b834 GlobalISel: Fix narrowScalar for G_{CTLZ|CTTZ}_ZERO_UNDEF adds 512c03bac44 [DebugInfo] Add a DWARFDataExtractor constructor that takes [...] adds 64f417200e1 [RISCV] Fix incorrect FP base CFI offset for variable argum [...] adds 05d44204fa1 [X86] Use MOVZX instead of MOVSX in f16_to_fp isel patterns. adds f24c43c0c50 [X86] Autogenerate complete checks. NFC adds a0678913898 [clang][codegen] Fix another lifetime emission on alloca on [...] adds ab3da5dd66c Fix `-Wparentheses` warning. NFC.
No new revisions were added by this update.
Summary of changes: clang/lib/CodeGen/CGCall.cpp | 8 +- clang/lib/CodeGen/CodeGenFunction.h | 5 +- clang/test/CodeGenCXX/amdgcn-call-with-aggarg.cpp | 19 + libclc/generic/include/clc/math/rsqrt.h | 8 +- libclc/generic/lib/SOURCES | 1 + libclc/generic/lib/math/rsqrt.cl | 23 + libclc/r600/lib/SOURCES | 2 + libclc/r600/lib/math/native_rsqrt.cl | 10 + libclc/r600/lib/math/rsqrt.cl | 23 + lldb/docs/resources/build.rst | 8 - lldb/docs/resources/test.rst | 4 +- lldb/docs/status/releases.rst | 9 +- lldb/docs/status/status.rst | 75 +- .../TestGdbRemoteLibrariesSvr4Support.py | 2 +- .../SymbolFile/DWARF/DWARFDataExtractor.cpp | 3 +- lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp | 4 +- .../llvm/DebugInfo/DWARF/DWARFDataExtractor.h | 5 + llvm/include/llvm/InitializePasses.h | 1 + llvm/include/llvm/LinkAllPasses.h | 1 + llvm/include/llvm/Transforms/Vectorize.h | 6 + .../llvm/Transforms/Vectorize/VectorCombine.h | 30 + llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 48 +- llvm/lib/DebugInfo/DWARF/DWARFDebugLoc.cpp | 2 +- llvm/lib/Passes/PassBuilder.cpp | 6 +- llvm/lib/Passes/PassRegistry.def | 1 + llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 1 - llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h | 1 - llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td | 3 - .../Target/AMDGPU/AMDGPUInstructionSelector.cpp | 6 + llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 24 +- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 41 +- llvm/lib/Target/AMDGPU/SIInstructions.td | 11 - llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp | 26 +- llvm/lib/Target/Mips/MipsLegalizerInfo.cpp | 2 + llvm/lib/Target/RISCV/RISCVFrameLowering.cpp | 4 +- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 67 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 135 +- llvm/lib/Target/X86/X86InstrAVX512.td | 659 +++-- llvm/lib/Target/X86/X86InstrCompiler.td | 16 - llvm/lib/Target/X86/X86InstrSSE.td | 2 +- llvm/lib/Transforms/IPO/OpenMPOpt.cpp | 6 +- llvm/lib/Transforms/IPO/PassManagerBuilder.cpp | 8 +- llvm/lib/Transforms/Vectorize/CMakeLists.txt | 1 + llvm/lib/Transforms/Vectorize/VectorCombine.cpp | 160 ++ llvm/lib/Transforms/Vectorize/Vectorize.cpp | 4 +- .../GlobalISel/inst-select-extract-vector-elt.mir | 55 + .../GlobalISel/inst-select-insert-vector-elt.mir | 63 + .../GlobalISel/legalize-extract-vector-elt.mir | 24 +- .../GlobalISel/legalize-insert-vector-elt.mir | 27 +- .../GlobalISel/regbankselect-ctlz-zero-undef.mir | 55 +- .../AMDGPU/GlobalISel/regbankselect-ctpop.mir | 55 +- .../GlobalISel/regbankselect-cttz-zero-undef.mir | 55 +- .../AMDGPU/si-if-lower-user-terminators.mir | 75 + .../CodeGen/Mips/GlobalISel/legalizer/ctlz.mir | 6 +- .../CodeGen/Mips/GlobalISel/legalizer/cttz.mir | 22 +- llvm/test/CodeGen/RISCV/vararg.ll | 8 +- llvm/test/CodeGen/X86/avx512-insert-extract.ll | 8 +- llvm/test/CodeGen/X86/avx512-vec-cmp.ll | 12 +- .../CodeGen/X86/fastmath-float-half-conversion.ll | 71 +- llvm/test/CodeGen/X86/half.ll | 28 +- llvm/test/CodeGen/X86/pr31088.ll | 12 +- llvm/test/CodeGen/X86/shl-crash-on-legalize.ll | 2 +- llvm/test/CodeGen/X86/vec_fp_to_int.ll | 4 +- llvm/test/CodeGen/X86/vector-half-conversions.ll | 436 +-- llvm/test/CodeGen/X86/vector-shuffle-128-v16.ll | 369 ++- llvm/test/CodeGen/X86/vector-shuffle-128-v8.ll | 378 ++- llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll | 2783 +++++++++++++++++++- llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll | 1829 ++++++++++++- llvm/test/CodeGen/X86/vector-shuffle-512-v32.ll | 18 + llvm/test/CodeGen/X86/vector-shuffle-512-v64.ll | 35 +- .../X86/vector-shuffle-combining-avx512bwvl.ll | 6 +- .../CodeGen/X86/vector-shuffle-combining-xop.ll | 6 +- llvm/test/Other/new-pm-defaults.ll | 4 + llvm/test/Other/new-pm-thinlto-defaults.ll | 4 + .../Other/new-pm-thinlto-postlink-pgo-defaults.ll | 4 + .../new-pm-thinlto-postlink-samplepgo-defaults.ll | 4 + llvm/test/Other/opt-O2-pipeline.ll | 4 + llvm/test/Other/opt-O3-pipeline.ll | 4 + llvm/test/Other/opt-Os-pipeline.ll | 4 + .../Transforms/VectorCombine/X86/extract-cmp.ll | 87 + .../VectorCombine}/X86/lit.local.cfg | 0 llvm/tools/llvm-readobj/DwarfCFIEHPrinter.h | 9 +- .../CodeGen/GlobalISel/LegalizerHelperTest.cpp | 70 + .../llvm/lib/Transforms/Vectorize/BUILD.gn | 1 + 84 files changed, 7207 insertions(+), 911 deletions(-) create mode 100644 clang/test/CodeGenCXX/amdgcn-call-with-aggarg.cpp create mode 100644 libclc/generic/lib/math/rsqrt.cl create mode 100644 libclc/r600/lib/math/native_rsqrt.cl create mode 100644 libclc/r600/lib/math/rsqrt.cl create mode 100644 llvm/include/llvm/Transforms/Vectorize/VectorCombine.h create mode 100644 llvm/lib/Transforms/Vectorize/VectorCombine.cpp create mode 100644 llvm/test/CodeGen/AMDGPU/si-if-lower-user-terminators.mir create mode 100644 llvm/test/Transforms/VectorCombine/X86/extract-cmp.ll copy llvm/test/{Analysis/CostModel => Transforms/VectorCombine}/X86/lit.local.cfg (100%)