This is an automated email from the git hooks/post-receive script.
tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-stable-allyesconfig in repository toolchain/ci/qemu.
from 48c03a0e13 Merge tag 's390x-2021-12-17' of https://gitlab.com/thuth/qem [...] adds 73944a4bf4 pseries: Update SLOF firmware image adds 2307ddc15b Merge tag 'qemu-slof-20211112' of github.com:aik/qemu into ppc-next adds 83234b8289 hw/ppc/mac.h: Remove MAX_CPUS macro adds c3a824b0cf target/ppc: Fixed call to deferred exception adds 00d3880251 test/tcg/ppc64le: test mtfsf adds 25ee608d79 target/ppc: ppc_store_fpscr doesn't update bits 0 to 28 and 52 adds 5f1470b091 target/ppc: Implement Vector Expand Mask adds 17868d81e0 target/ppc: Implement Vector Extract Mask adds 9193eaa901 target/ppc: Implement Vector Mask Move insns adds ef80a708b5 ivshmem.c: change endianness to LITTLE_ENDIAN adds d04aeb6862 ivshmem-test.c: enable test_ivshmem_server for ppc64 arch adds fa4b5eaaf9 pci-host: Allow extended config space access for PowerNV PHB4 model adds 58c49ef5c4 docs: Minor updates on the powernv documentation. adds ebe6c3fab8 ppc/pnv.c: add a friendly warning when accel=kvm is used adds 3e8f715815 docs/system/ppc/powernv.rst: document KVM support status adds bbfbbff5fc ppc/pnv.c: fix "system-id" FDT when -uuid is set adds 88581cc43b docs: Introducing pseries documentation. adds d483f2b53a docs: rSTify ppc-spapr-hcalls.txt adds d55b123d14 docs: Rename ppc-spapr-hcalls.txt to ppc-spapr-hcalls.rst. adds 9befbe4f62 Link new ppc-spapr-hcalls.rst file to pseries.rst. adds 149a48f6e6 softfloat: Extend float_exception_flags to 16 bits adds ba11446c40 softfloat: Add flag specific to Inf - Inf adds bead3c9b0f softfloat: Add flag specific to Inf * 0 adds 10cc964030 softfloat: Add flags specific to Inf / Inf and 0 / 0 adds f8718aab89 softfloat: Add flag specific to sqrt(-x) adds 81254b02eb softfloat: Add flag specific to convert non-nan to int adds e706d4455b softfloat: Add flag specific to signaling nans adds 941298ecd7 target/ppc: Update float_invalid_op_addsub for new flags adds 4edf55698f target/ppc: Update float_invalid_op_mul for new flags adds c07f82416c target/ppc: Update float_invalid_op_div for new flags adds f2e2504676 target/ppc: Move float_check_status from FPU_FCTI to translate adds 353464ea16 target/ppc: Update float_invalid_cvt for new flags adds fed12f3b2d target/ppc: Fix VXCVI return value adds b891757e44 target/ppc: Remove inline from do_fri adds 6bce077777 target/ppc: Use FloatRoundMode in do_fri adds 1348d20b16 target/ppc: Tidy inexact handling in do_fri adds a496352736 target/ppc: Clean up do_fri adds e4052bb773 target/ppc: Update fmadd for new flags adds ffdaff8e9c target/ppc: Split out do_fmadd adds 2125ac18bf target/ppc: Do not call do_float_check_status from do_fmadd adds 7238e55bd6 target/ppc: Split out do_frsp adds 734cfbd84e target/ppc: Update do_frsp for new flags adds 58c7edef61 target/ppc: Use helper_todouble in do_frsp adds 3d3050cc8d target/ppc: Update sqrt for new flags adds 053e23a694 target/ppc: Update xsrqpi and xsrqpxp to new flags adds 8ea0b1408e target/ppc: Update fre to new flags adds 42636fb923 softfloat: Add float64r32 arithmetic routines adds d04ca895dc target/ppc: Add helpers for fmadds et al adds 41ae890d08 target/ppc: Add helper for fsqrts adds d9e792a1c1 target/ppc: Add helpers for fadds, fsubs, fdivs adds 7f87214e3b target/ppc: Add helper for fmuls adds dedbfda765 target/ppc: Add helper for frsqrtes adds 7d82ea3484 target/ppc: Update fres to new flags and float64r32 adds a1f1c731c6 target/ppc: Use helper_todouble/tosingle in helper_xststdcsp adds 1da666cd8e target/ppc: Disable software TLB for the 7450 family adds b137fb72d7 target/ppc: Disable unused facilities in the e600 CPU adds a09410ed1f target/ppc: Remove the software TLB model of 7450 CPUs adds 6328a3bb4b target/ppc: Fix MPCxxx FPU interrupt address adds fd77f75710 target/ppc: Remove 603e exception model adds 84835acbbf target/ppc: Set 601v exception model id adds c8f49e6b93 target/ppc: remove 401/403 CPUs adds 82f64c2384 ppc/ppc405: Change kernel load address adds 26e8bed611 ppc: Mark the 'taihu' machine as deprecated adds de82dabead ppc: Add trace-events for DCR accesses adds 09960a5be3 ppc/ppc405: Convert printfs to trace-events adds af9e361512 ppc/ppc405: Drop flag parameter in ppc405_set_bootinfo() adds a3e973e1bf ppc/ppc405: Change ppc405ep_init() return value adds f61b99d35e ppc/ppc405: Add some address space definitions adds 9fb100efa1 ppc/ppc405: Remove flash support adds 13d63de59b ppc/ppc405: Rework FW load adds e3931ecab3 ppc/ppc405: Introduce ppc405_set_default_bootinfo() adds 337270b2a5 ppc/ppc405: Fix boot from kernel adds cada9f30d3 ppc/ppc405: Change default PLL values at reset adds e0caa8e64d ppc/ppc405: Fix bi_pci_enetaddr2 field in U-Boot board information adds 6518c0ede9 ppc/ppc405: Add update of bi_procfreq field adds 201fc774e0 target/ppc: Fix xs{max, min}[cj]dp to use VSX registers adds c5df1898a1 target/ppc: Move xs{max,min}[cj]dp to decodetree adds 38d4914c50 target/ppc: fix xscvqpdp register access adds caf6f9b568 target/ppc: move xscvqpdp to decodetree adds 7fc1dc8313 target/ppc: Fix e6500 boot adds 29c4a3363b Revert "target/ppc: Move SPR_DSISR setting to powerpc_excp" adds 8f2e9d4003 target/ppc: introduce PMUEventType and PMU overflow timers adds c2eff582a3 target/ppc: PMU basic cycle count for pseries TCG adds 308b9fad2a target/ppc: PMU: update counters on PMCs r/w adds a6f91249e0 target/ppc: PMU: update counters on MMCR1 write adds 1474ba6d10 target/ppc: enable PMU counter overflow with cycle events adds 46d396bde9 target/ppc: enable PMU instruction count adds 7aeac354a6 target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) event adds 1f26c75191 PPC64/TCG: Implement 'rfebb' instruction adds 2c4d3a501e ppc/pnv: Introduce a "chip" property under PHB3 adds a8fa95c7e6 ppc/pnv: Use the chip class to check the index of PHB3 devices adds 9e59b09ccf ppc/pnv: Drop the "num-phbs" property adds 10841a76eb ppc/pnv: Move mapping of the PHB3 CQ regions under pnv_pbcq_ [...] adds 2ff73dda02 ppc/pnv: Use QOM hierarchy to scan PHB3 devices adds 422fd92e61 ppc/pnv: Introduce a num_pecs class attribute for PHB4 PEC devices adds 12060cbd3f ppc/pnv: Introduce version and device_id class atributes for [...] adds 6f43d2551f ppc/pnv: Introduce a "chip" property under the PHB4 model adds cf0ee6955c ppc/pnv: Introduce a num_stack class attribute adds aa8cc84d88 ppc/pnv: Compute the PHB index from the PHB4 PEC model adds 8da4f8f7b7 ppc/pnv: Remove "system-memory" property from PHB4 PEC adds 13480fc58a ppc/pnv: Move realize of PEC stacks under the PEC model adds 0e6232bc3c ppc/pnv: Use QOM hierarchy to scan PEC PHB4 devices adds 93dc314c92 Merge tag 'pull-ppc-20211217' of https://github.com/legoater [...] adds 57a93f16e8 configure: Symlink binaries using .exe suffix with MinGW adds dc7d6cafce target/i386/kvm: Replace use of __u32 type adds 4455922f7b qemu-keymap: Add license in generated files adds 74fb2f4f4c hw/avr: Realize AVRCPU qdev object using qdev_realize() adds f71d31fa81 hw/virtio/vhost: Fix typo in comment. adds 036ef344b6 docs/block-replication.txt: Fix replication top-id command demo adds 2c674fada7 glib-compat: Introduce g_memdup2() wrapper adds 460056dbe6 tests/qtest: Replace g_memdup() by g_memdup2() adds ce2ff9cccf checkpatch: Do not allow deprecated g_memdup() adds 90978e15bc Merge tag 'trivial-branch-for-7.0-pull-request' of https://g [...] adds ba7c60c203 configure: make $targetos lowercase, use windows instead of MINGW32 adds 65eff01bcf configure: move target detection before CPU detection adds e4da0e39df configure: unify two case statements on $cpu adds d8ff892dc2 configure: unify ppc64 and ppc64le adds 4da270be1c configure: unify x86_64 and x32 adds ffb91f68b1 meson: rename "arch" variable adds 823eb01345 configure, meson: move ARCH to meson.build adds 0f457147f4 configure: remove unnecessary symlinks adds 5dce7b8d8c configure: remove DIRS adds 7a82413dbd meson: reenable test-fdmon-epoll adds ad5439bb53 cpu: remove unnecessary #ifdef CONFIG_TCG adds b20a7ee6f0 meson: add "check" argument to run_command adds 7a3ce79c06 hw/scsi: Fix scsi_bus_init_named() docstring adds 97a2b074d1 hw/scsi/megasas: Fails command if SGL buffer overflows adds 08c34c642d tests/qtest/fuzz-megasas-test: Add test for GitLab issue #521 adds 5a3a2eb3b1 hw/i386/vmmouse: Require 'i8042' property to be set adds 212a33d3b0 Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu [...] adds 915f77b211 target/riscv: zfh: half-precision load and store adds 00c1899f12 target/riscv: zfh: half-precision computational adds 7b03c8e5b5 target/riscv: zfh: half-precision convert and move adds 11f9c450a6 target/riscv: zfh: half-precision floating-point compare adds 6bc6fc96d1 target/riscv: zfh: half-precision floating-point classify adds 13fb8c7b42 target/riscv: zfh: add Zfh cpu property adds 2d258b428b target/riscv: zfh: implement zfhmin extension adds e523773040 target/riscv: zfh: add Zfhmin cpu property adds 9ec6622db3 target/riscv: drop vector 0.7.1 and add 1.0 support adds 52561f2a80 target/riscv: Use FIELD_EX32() to extract wd field adds 61b4b69d12 target/riscv: rvv-1.0: add mstatus VS field adds c36b2f1a4d target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty adds 89a81e376a target/riscv: rvv-1.0: add sstatus VS field adds 7b07a37c2c target/riscv: rvv-1.0: introduce writable misa.v field adds 8e1ee1fb57 target/riscv: rvv-1.0: add translation-time vector context status adds 9bd291f6e3 target/riscv: rvv-1.0: remove rvv related codes from fcsr registers adds 4594fa5a96 target/riscv: rvv-1.0: add vcsr register adds 2e56505475 target/riscv: rvv-1.0: add vlenb register adds 6bc3dfa96d target/riscv: rvv-1.0: check MSTATUS_VS when accessing vecto [...] adds f9298de514 target/riscv: rvv-1.0: remove MLEN calculations adds 33f1beaf12 target/riscv: rvv-1.0: add fractional LMUL adds 3479a814e4 target/riscv: rvv-1.0: add VMA and VTA adds f31dacd720 target/riscv: rvv-1.0: update check functions adds ff64fc91d1 target/riscv: introduce more imm value modes in translator f [...] adds 9b4a40a786 target/riscv: rvv:1.0: add translation-time nan-box helper function adds 57a2d89a82 target/riscv: rvv-1.0: remove amo operations instructions adds d9b7609a1f target/riscv: rvv-1.0: configure instructions adds 79556fb6fa target/riscv: rvv-1.0: stride load and store instructions adds 08b9d0ed4a target/riscv: rvv-1.0: index load and store instructions adds 83fcd573b1 target/riscv: rvv-1.0: fix address index overflow bug of ind [...] adds d3e5e2ff4f target/riscv: rvv-1.0: fault-only-first unit stride load adds 30206bd842 target/riscv: rvv-1.0: load/store whole register instructions adds 5a9f8e1552 target/riscv: rvv-1.0: update vext_max_elems() for load/store insns adds a689a82b7f target/riscv: rvv-1.0: take fractional LMUL into vector max [...] adds 20f2079acf target/riscv: rvv-1.0: floating-point square-root instruction adds 0676d8e3dc target/riscv: rvv-1.0: floating-point classify instructions adds 0014aa741d target/riscv: rvv-1.0: count population in mask instruction adds d71a24fc82 target/riscv: rvv-1.0: find-first-set mask bit instruction adds 40c1495d69 target/riscv: rvv-1.0: set-X-first mask bit instructions adds ee17eaa120 target/riscv: rvv-1.0: iota instruction adds f4f47e04de target/riscv: rvv-1.0: element index instruction adds 308ee80578 target/riscv: rvv-1.0: allow load element with sign-extended adds 50bfb45b2c target/riscv: rvv-1.0: register gather instructions adds dedc53cbc9 target/riscv: rvv-1.0: integer scalar move instructions adds c4b3e46f00 target/riscv: rvv-1.0: floating-point move instruction adds 5c4eb8fb56 target/riscv: rvv-1.0: floating-point scalar move instructions adds 6b85975e11 target/riscv: rvv-1.0: whole register move instructions adds cd01340e75 target/riscv: rvv-1.0: integer extension instructions adds 8b99a110f7 target/riscv: rvv-1.0: single-width averaging add and subtra [...] adds a75ae09f2a target/riscv: rvv-1.0: single-width bit shift instructions adds bb45485ad1 target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow adds 7daa5852bc target/riscv: rvv-1.0: narrowing integer right shift instructions adds f51c3cf1fa target/riscv: rvv-1.0: widening integer multiply-add instructions adds d6be7a3504 target/riscv: rvv-1.0: single-width saturating add and subtr [...] adds 063f8bbca0 target/riscv: rvv-1.0: integer comparison instructions adds e70aa16e5e target/riscv: rvv-1.0: floating-point compare instructions adds 50f6696c0f target/riscv: rvv-1.0: mask-register logical instructions adds 6438ed61de target/riscv: rvv-1.0: slide instructions adds 8500d4ab2e target/riscv: rvv-1.0: floating-point slide instructions adds a70b3a73e7 target/riscv: rvv-1.0: narrowing fixed-point clip instructions adds 08b60eebc4 target/riscv: rvv-1.0: single-width floating-point reduction adds b8dd99f2d1 target/riscv: rvv-1.0: widening floating-point reduction ins [...] adds 74eb7834bc target/riscv: rvv-1.0: single-width scaling shift instructions adds a12c812d19 target/riscv: rvv-1.0: remove widening saturating scaled mul [...] adds e29c5cefd8 target/riscv: rvv-1.0: remove vmford.vv and vmford.vf adds c3536f2f55 target/riscv: rvv-1.0: remove integer extract instruction adds 49c5611a97 target/riscv: rvv-1.0: floating-point min/max instructions adds 986c895de1 target/riscv: introduce floating-point rounding mode enum adds 900da87ab9 target/riscv: rvv-1.0: floating-point/integer type-convert i [...] adds 3ce4c09df7 target/riscv: rvv-1.0: widening floating-point/integer type-convert adds 75804f7131 target/riscv: add "set round to odd" rounding mode helper function adds ff679b58e3 target/riscv: rvv-1.0: narrowing floating-point/integer type [...] adds 8a4b52575a target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits adds f714361ed7 target/riscv: rvv-1.0: implement vstart CSR adds d6c4d3f2a6 target/riscv: rvv-1.0: trigger illegal instruction exception [...] adds 719d3561b2 target/riscv: gdb: support vector registers for rv64 & rv32 adds e848a1e563 target/riscv: rvv-1.0: floating-point reciprocal square-root [...] adds 55c35407c3 target/riscv: rvv-1.0: floating-point reciprocal estimate in [...] adds 6b5c8eb3e7 target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11 adds 34a2c2d81a target/riscv: rvv-1.0: add vsetivli instruction adds 5c89e9c096 target/riscv: rvv-1.0: add evl parameter to vext_ldst_us() adds 26086aea0d target/riscv: rvv-1.0: add vector unit-stride mask load/store insns adds 9c0d2559de target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to [...] adds 45ca2ca6bd target/riscv: rvv-1.0: update opivv_vadc_check() comment adds cc13aa3614 target/riscv: rvv-1.0: Add ELEN checks for widening and narr [...] adds a7cad953fa riscv: Set 5.4 as minimum kernel version for riscv32 adds 0643c12e4b target/riscv: Enable bitmanip Zb[abcs] instructions adds 7e322a7f23 hw/riscv: Use load address rather than entry point for fw_dy [...] adds c7d773ae49 Merge tag 'pull-riscv-to-apply-20211220-1' of github.com:ali [...] adds b9d2af3c62 linux-user: Untabify all safe-syscall.inc.S adds a3310c0397 linux-user: Move syscall error detection into safe_syscall_base adds 4542adef5b linux-user/host/mips: Add safe-syscall.inc.S adds 95c021dac8 linux-user/host/sparc64: Add safe-syscall.inc.S adds 0a7e01904d linux-user: Remove HAVE_SAFE_SYSCALL and hostdep.h adds af254a2792 linux-user: Rename TARGET_ERESTARTSYS to QEMU_ERESTARTSYS adds ea8ee3ee93 bsd-user: Rename TARGET_ERESTARTSYS to QEMU_ERESTARTSYS adds 57a0c9384c linux-user: Rename TARGET_QEMU_ESIGRETURN to QEMU_ESIGRETURN adds 5da4063f64 linux-user: Create special-errno.h adds 2ac16d01e3 bsd-user: Create special-errno.h adds bbf15aaf7c common-user: Move safe-syscall.* from linux-user adds 5bfd125ec8 common-user: Adjust system call return on FreeBSD adds ff9c1e5500 linux-user: Move thunk.c from top-level adds 4d06bb4e03 meson: Move linux_user_ss to linux-user/ adds 3363615a65 meson: Move bsd_user_ss to bsd-user/ adds 2bf40d0841 Merge tag 'pull-user-20211220' of https://gitlab.com/rth7680 [...]
No new revisions were added by this update.
Summary of changes: MAINTAINERS | 3 +- bsd-user/errno_defs.h | 6 +- bsd-user/meson.build | 6 + bsd-user/special-errno.h | 24 + common-user/host/aarch64/safe-syscall.inc.S | 88 + common-user/host/arm/safe-syscall.inc.S | 108 + common-user/host/i386/safe-syscall.inc.S | 126 + common-user/host/mips/safe-syscall.inc.S | 148 + common-user/host/ppc64/safe-syscall.inc.S | 94 + common-user/host/riscv/safe-syscall.inc.S | 79 + common-user/host/s390x/safe-syscall.inc.S | 98 + common-user/host/sparc64/safe-syscall.inc.S | 89 + .../host/x86_64/safe-syscall.inc.S | 42 +- common-user/meson.build | 6 + common-user/safe-syscall-error.c | 25 + {linux-user => common-user}/safe-syscall.S | 5 +- configure | 255 +- cpu.c | 5 - docs/about/deprecated.rst | 9 + docs/block-replication.txt | 2 +- docs/meson.build | 6 +- docs/specs/ppc-spapr-hcalls.rst | 100 + docs/specs/ppc-spapr-hcalls.txt | 78 - docs/system/ppc/powernv.rst | 68 +- docs/system/ppc/pseries.rst | 226 ++ fpu/softfloat-parts.c.inc | 57 +- fpu/softfloat-specialize.c.inc | 12 +- fpu/softfloat.c | 114 +- hw/avr/atmega.c | 2 +- hw/i386/vmmouse.c | 4 + hw/misc/ivshmem.c | 2 +- hw/pci-host/pnv_phb3.c | 3 +- hw/pci-host/pnv_phb3_pbcq.c | 11 + hw/pci-host/pnv_phb4.c | 1 + hw/pci-host/pnv_phb4_pec.c | 75 +- hw/ppc/mac.h | 3 - hw/ppc/mac_newworld.c | 3 +- hw/ppc/mac_oldworld.c | 3 +- hw/ppc/pnv.c | 177 +- hw/ppc/ppc.c | 2 + hw/ppc/ppc405.h | 14 +- hw/ppc/ppc405_boards.c | 245 +- hw/ppc/ppc405_uc.c | 225 +- hw/ppc/spapr_cpu_core.c | 1 + hw/ppc/trace-events | 23 + hw/riscv/boot.c | 13 +- hw/scsi/megasas.c | 1 + hw/virtio/vhost.c | 2 +- include/exec/cpu-all.h | 2 - include/fpu/softfloat-types.h | 23 +- include/fpu/softfloat.h | 14 +- include/glib-compat.h | 37 + include/hw/pci-host/pnv_phb3.h | 3 + include/hw/pci-host/pnv_phb4.h | 5 + include/hw/ppc/pnv.h | 2 + include/hw/scsi/scsi.h | 2 +- {linux-user => include/user}/safe-syscall.h | 37 +- linux-user/aarch64/cpu_loop.c | 4 +- linux-user/aarch64/signal.c | 4 +- linux-user/alpha/cpu_loop.c | 4 +- linux-user/alpha/signal.c | 8 +- linux-user/arm/cpu_loop.c | 4 +- linux-user/arm/signal.c | 8 +- linux-user/cpu_loop-common.h | 1 + linux-user/cris/cpu_loop.c | 4 +- linux-user/cris/signal.c | 4 +- linux-user/generic/target_errno_defs.h | 17 - linux-user/hexagon/cpu_loop.c | 4 +- linux-user/hexagon/signal.c | 2 +- linux-user/host/aarch64/hostdep.h | 18 - linux-user/host/aarch64/safe-syscall.inc.S | 75 - linux-user/host/arm/hostdep.h | 18 - linux-user/host/arm/safe-syscall.inc.S | 90 - linux-user/host/i386/hostdep.h | 18 - linux-user/host/i386/safe-syscall.inc.S | 100 - linux-user/host/ia64/hostdep.h | 15 - linux-user/host/mips/hostdep.h | 15 - linux-user/host/ppc/hostdep.h | 15 - linux-user/host/ppc64/hostdep.h | 18 - linux-user/host/ppc64/safe-syscall.inc.S | 96 - linux-user/host/riscv/hostdep.h | 14 - linux-user/host/riscv/safe-syscall.inc.S | 77 - linux-user/host/s390/hostdep.h | 15 - linux-user/host/s390x/hostdep.h | 18 - linux-user/host/s390x/safe-syscall.inc.S | 90 - linux-user/host/sparc/hostdep.h | 15 - linux-user/host/sparc64/hostdep.h | 15 - linux-user/host/x32/hostdep.h | 15 - linux-user/host/x86_64/hostdep.h | 18 - linux-user/hppa/cpu_loop.c | 4 +- linux-user/hppa/signal.c | 4 +- linux-user/i386/cpu_loop.c | 12 +- linux-user/i386/signal.c | 8 +- linux-user/m68k/cpu_loop.c | 4 +- linux-user/m68k/signal.c | 8 +- linux-user/meson.build | 9 +- linux-user/microblaze/cpu_loop.c | 4 +- linux-user/microblaze/signal.c | 4 +- linux-user/mips/cpu_loop.c | 4 +- linux-user/mips/signal.c | 8 +- linux-user/openrisc/cpu_loop.c | 4 +- linux-user/ppc/cpu_loop.c | 4 +- linux-user/ppc/signal.c | 10 +- linux-user/riscv/cpu_loop.c | 4 +- linux-user/riscv/signal.c | 2 +- linux-user/riscv/target_syscall.h | 3 +- linux-user/s390x/cpu_loop.c | 4 +- linux-user/s390x/signal.c | 8 +- linux-user/sh4/cpu_loop.c | 4 +- linux-user/sh4/signal.c | 8 +- linux-user/signal-common.h | 4 +- linux-user/signal.c | 10 +- linux-user/sparc/cpu_loop.c | 2 +- linux-user/sparc/signal.c | 8 +- linux-user/special-errno.h | 32 + linux-user/syscall.c | 21 +- thunk.c => linux-user/thunk.c | 0 linux-user/user-internals.h | 1 - linux-user/xtensa/cpu_loop.c | 4 +- linux-user/xtensa/signal.c | 4 +- meson.build | 60 +- pc-bios/README | 2 +- pc-bios/meson.build | 2 +- pc-bios/slof.bin | Bin 991744 -> 991920 bytes qemu-keymap.c | 1 + roms/SLOF | 2 +- scripts/checkpatch.pl | 5 + target/i386/kvm/kvm.c | 2 +- target/ppc/cpu-models.c | 34 - target/ppc/cpu-models.h | 19 - target/ppc/cpu-qom.h | 12 +- target/ppc/cpu.c | 2 +- target/ppc/cpu.h | 63 +- target/ppc/cpu_init.c | 658 +--- target/ppc/excp_helper.c | 95 +- target/ppc/fpu_helper.c | 593 ++-- target/ppc/helper.h | 29 +- target/ppc/helper_regs.c | 7 + target/ppc/insn32.decode | 54 +- target/ppc/meson.build | 1 + target/ppc/mmu_common.c | 60 +- target/ppc/mmu_helper.c | 32 - target/ppc/power8-pmu-regs.c.inc | 69 +- target/ppc/power8-pmu.c | 350 ++ target/ppc/power8-pmu.h | 26 + target/ppc/spr_tcg.h | 5 + target/ppc/translate.c | 104 +- target/ppc/translate/branch-impl.c.inc | 33 + target/ppc/translate/fp-impl.c.inc | 53 +- target/ppc/translate/vmx-impl.c.inc | 231 ++ target/ppc/translate/vsx-impl.c.inc | 55 +- target/ppc/translate/vsx-ops.c.inc | 5 - target/riscv/cpu.c | 28 +- target/riscv/cpu.h | 63 +- target/riscv/cpu_bits.h | 10 + target/riscv/cpu_helper.c | 39 +- target/riscv/csr.c | 63 +- target/riscv/fpu_helper.c | 197 +- target/riscv/gdbstub.c | 184 + target/riscv/helper.h | 464 ++- target/riscv/insn32.decode | 332 +- target/riscv/insn_trans/trans_rvv.c.inc | 2429 ++++++++----- target/riscv/insn_trans/trans_rvzfh.c.inc | 537 +++ target/riscv/internals.h | 40 +- target/riscv/translate.c | 93 +- target/riscv/vector_helper.c | 3601 ++++++++++---------- tests/qtest/fuzz-megasas-test.c | 30 + tests/qtest/ivshmem-test.c | 5 +- tests/qtest/libqos/ahci.c | 6 +- tests/qtest/libqos/qgraph.c | 2 +- tests/tcg/configure.sh | 4 +- tests/tcg/ppc64/Makefile.target | 1 + tests/tcg/ppc64le/Makefile.target | 1 + tests/tcg/ppc64le/mtfsf.c | 61 + tests/unit/meson.build | 2 +- 175 files changed, 8833 insertions(+), 5862 deletions(-) create mode 100644 bsd-user/special-errno.h create mode 100644 common-user/host/aarch64/safe-syscall.inc.S create mode 100644 common-user/host/arm/safe-syscall.inc.S create mode 100644 common-user/host/i386/safe-syscall.inc.S create mode 100644 common-user/host/mips/safe-syscall.inc.S create mode 100644 common-user/host/ppc64/safe-syscall.inc.S create mode 100644 common-user/host/riscv/safe-syscall.inc.S create mode 100644 common-user/host/s390x/safe-syscall.inc.S create mode 100644 common-user/host/sparc64/safe-syscall.inc.S rename {linux-user => common-user}/host/x86_64/safe-syscall.inc.S (81%) create mode 100644 common-user/meson.build create mode 100644 common-user/safe-syscall-error.c rename {linux-user => common-user}/safe-syscall.S (91%) create mode 100644 docs/specs/ppc-spapr-hcalls.rst delete mode 100644 docs/specs/ppc-spapr-hcalls.txt rename {linux-user => include/user}/safe-syscall.h (83%) delete mode 100644 linux-user/host/aarch64/hostdep.h delete mode 100644 linux-user/host/aarch64/safe-syscall.inc.S delete mode 100644 linux-user/host/arm/hostdep.h delete mode 100644 linux-user/host/arm/safe-syscall.inc.S delete mode 100644 linux-user/host/i386/hostdep.h delete mode 100644 linux-user/host/i386/safe-syscall.inc.S delete mode 100644 linux-user/host/ia64/hostdep.h delete mode 100644 linux-user/host/mips/hostdep.h delete mode 100644 linux-user/host/ppc/hostdep.h delete mode 100644 linux-user/host/ppc64/hostdep.h delete mode 100644 linux-user/host/ppc64/safe-syscall.inc.S delete mode 100644 linux-user/host/riscv/hostdep.h delete mode 100644 linux-user/host/riscv/safe-syscall.inc.S delete mode 100644 linux-user/host/s390/hostdep.h delete mode 100644 linux-user/host/s390x/hostdep.h delete mode 100644 linux-user/host/s390x/safe-syscall.inc.S delete mode 100644 linux-user/host/sparc/hostdep.h delete mode 100644 linux-user/host/sparc64/hostdep.h delete mode 100644 linux-user/host/x32/hostdep.h delete mode 100644 linux-user/host/x86_64/hostdep.h create mode 100644 linux-user/special-errno.h rename thunk.c => linux-user/thunk.c (100%) create mode 100644 target/ppc/power8-pmu.c create mode 100644 target/ppc/power8-pmu.h create mode 100644 target/ppc/translate/branch-impl.c.inc create mode 100644 target/riscv/insn_trans/trans_rvzfh.c.inc create mode 100644 tests/tcg/ppc64le/mtfsf.c