[Tcwg-commits] [gcc] branch hsa updated (aab1e47 -> 76f6d19)

This is an automated email from the git hooks/post-receive script.

unknown user pushed a change to branch hsa in repository gcc.

from aab1e47 HSA: come up with a proper constructor of hsa_symbol. new 76a2ed2 HSA: add missing files removed in a merge commit. new 76f6d19 HSA: fix superfluous whitespaces

The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.

Summary of changes: gcc/c-family/ChangeLog.hsa | 5 ++++ gcc/c-family/c-common.c | 1 + gcc/cgraph.h | 2 +- gcc/testsuite/gcc.target/arm/simd/vextQf32_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vextQp16_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vextQp64_1.c | 31 ++++++++++++++++++++++++ gcc/testsuite/gcc.target/arm/simd/vextQp8_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vextQs16_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vextQs32_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vextQs64_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vextQs8_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vextQu16_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vextQu32_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vextQu64_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vextQu8_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vextf32_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vextp16_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vextp64_1.c | 24 ++++++++++++++++++ gcc/testsuite/gcc.target/arm/simd/vextp8_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vexts16_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vexts32_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vexts8_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vextu16_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vextu32_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vextu8_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev16p8_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev16qp8_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev16qs8_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev16qu8_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev16s8_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev16u8_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev32p16_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev32p8_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev32qp16_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev32qp8_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev32qs16_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev32qs8_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev32qu16_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev32qu8_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev32s16_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev32s8_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev32u16_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev32u8_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev64f32_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev64p16_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev64p8_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev64qf32_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev64qp16_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev64qp8_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev64qs16_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev64qs32_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev64qs8_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev64qu16_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev64qu32_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev64qu8_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev64s16_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev64s32_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev64s8_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev64u16_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev64u32_1.c | 9 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev64u8_1.c | 9 +++++++ 61 files changed, 566 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/arm/simd/vextQf32_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vextQp16_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vextQp64_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vextQp8_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vextQs16_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vextQs32_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vextQs64_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vextQs8_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vextQu16_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vextQu32_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vextQu64_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vextQu8_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vextf32_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vextp16_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vextp64_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vextp8_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vexts16_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vexts32_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vexts8_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vextu16_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vextu32_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vextu8_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev16p8_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev16qp8_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev16qs8_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev16qu8_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev16s8_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev16u8_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev32p16_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev32p8_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev32qp16_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev32qp8_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev32qs16_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev32qs8_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev32qu16_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev32qu8_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev32s16_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev32s8_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev32u16_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev32u8_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev64f32_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev64p16_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev64p8_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev64qf32_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev64qp16_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev64qp8_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev64qs16_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev64qs32_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev64qs8_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev64qu16_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev64qu32_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev64qu8_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev64s16_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev64s32_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev64s8_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev64u16_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev64u32_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev64u8_1.c