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from c6fce1250e5 [AMDGPU] gfx10 conditional registers handling new d116e8400b5 AMDGPU/GFX10: Support DLC bit in llvm.amdgcn.s.buffer.load [...]
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Summary of changes: include/llvm/IR/IntrinsicsAMDGPU.td | 2 +- lib/Target/AMDGPU/SIISelLowering.cpp | 16 ++++--- lib/Target/AMDGPU/SIISelLowering.h | 2 +- lib/Target/AMDGPU/SIInstrInfo.td | 3 +- lib/Target/AMDGPU/SMInstructions.td | 14 +++--- test/CodeGen/AMDGPU/smrd-gfx10.ll | 37 ++++++++++++++++ test/CodeGen/AMDGPU/smrd.ll | 85 ++++++++++++++++++------------------ 7 files changed, 103 insertions(+), 56 deletions(-) create mode 100644 test/CodeGen/AMDGPU/smrd-gfx10.ll