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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-next-defconfig in repository toolchain/ci/qemu.
from 9b1f588549 Merge tag 'pull-la-20220606' of https://gitlab.com/rth7680/q [...] adds 4d84bb6c8b hw/tpm/tpm_tis_common.c: Assert that locty is in range adds e37a0ef460 tpm_crb: mark command buffer as dirty on request completion adds 6d940eff47 Merge tag 'pull-tpm-2022-06-07-1' of https://github.com/stef [...] adds ec6600be0d vfio/common: remove spurious warning on vfio_listener_region_del adds 05911658cb Merge tag 'vfio-updates-20220608.0' of https://gitlab.com/al [...] adds d507bc3b05 target/arm: Declare support for FEAT_RASv1p1 adds 7ac610206a target/arm: Implement FEAT_DoubleFault adds 9323e79f10 Fix 'writeable' typos adds d2008b3355 xlnx_dp: fix the wrong register size adds 759ae1b47e xlnx_dp: Introduce a vblank signal adds 39f40d02f6 xlnx_dp: Fix the interrupt disable logic adds b3f5cc3fda xlnx-zynqmp: fix the irq mapping for the display port and its dma adds d8cca960a9 target/arm: Move stage_1_mmu_idx decl to internals.h adds 8ae0886002 target/arm: Move get_phys_addr to ptw.c adds f2d2f5ceb8 target/arm: Move get_phys_addr_v5 to ptw.c adds 53c038efb7 target/arm: Move get_phys_addr_v6 to ptw.c adds 9a12fb366d target/arm: Move get_phys_addr_pmsav5 to ptw.c adds 7d2e08c960 target/arm: Move get_phys_addr_pmsav7_default to ptw.c adds 1f2e87e5ab target/arm: Move get_phys_addr_pmsav7 to ptw.c adds 730d5c31d8 target/arm: Move get_phys_addr_pmsav8 to ptw.c adds fedbaa0503 target/arm: Move pmsav8_mpu_lookup to ptw.c adds c8e436c9f7 target/arm: Move pmsav7_use_background_region to ptw.c adds 2c1f429df3 target/arm: Move v8m_security_lookup to ptw.c adds 47ff5ba9d0 target/arm: Move m_is_{ppb,system}_region to ptw.c adds 4c74ab157b target/arm: Move get_level1_table_address to ptw.c adds 966f4bb7d8 target/arm: Move combine_cacheattrs and subroutines to ptw.c adds 3283222acd target/arm: Move get_phys_addr_lpae to ptw.c adds 11552bb0d9 target/arm: Move arm_{ldl,ldq}_ptw to ptw.c adds cd6bc4d517 target/arm: Move {arm_s1_, }regime_using_lpae_format to tlb_ [...] adds 1c73d84807 target/arm: Move arm_pamax, pamax_map into ptw.c adds f8526edc2f target/arm: Move get_S1prot, get_S2prot to ptw.c adds c5168785d2 target/arm: Move check_s2_mmu_setup to ptw.c adds 2f0ec92e94 target/arm: Move aa32_va_parameters to ptw.c adds 4845d3be12 target/arm: Move ap_to_tw_prot etc to ptw.c adds 0c23d56fc1 target/arm: Move regime_is_user to ptw.c adds 3b318aaeef target/arm: Move regime_ttbr to ptw.c adds 8db1a3a0bb target/arm: Move regime_translation_disabled to ptw.c adds 23971205cf target/arm: Move arm_cpu_get_phys_page_attrs_debug to ptw.c adds 1d26125536 target/arm: Move stage_1_mmu_idx, arm_stage1_mmu_idx to ptw.c adds 5e79887ba6 target/arm: Pass CPUARMState to arm_ld[lq]_ptw adds f45ce4c35f target/arm: Rename TBFLAG_A64 ZCR_LEN to VL adds 8b599e5c02 linux-user/aarch64: Introduce sve_vq adds 61a8c23a3b target/arm: Remove route_to_el2 check from sve_exception_el adds 397d922c62 target/arm: Remove fp checks from sve_exception_el adds 19668718ad target/arm: Add el_is_in_host adds c6225bebc2 target/arm: Use el_is_in_host for sve_zcr_len_for_el adds aa4451b60e target/arm: Use el_is_in_host for sve_exception_el adds 7d38cb92aa target/arm: Hoist arm_is_el2_enabled check in sve_exception_el adds 87252bdecd target/arm: Do not use aarch64_sve_zcr_get_valid_len in reset adds 9b5f422559 target/arm: Merge aarch64_sve_zcr_get_valid_len into caller adds 886902ece7 target/arm: Use uint32_t instead of bitmap for sve vq's adds 5ef3cc5636 target/arm: Rename sve_zcr_len_for_el to sve_vqm1_for_el adds d1ce862602 target/arm: Split out load/store primitives to sve_ldst_internal.h adds 0b68112b39 target/arm: Export sve contiguous ldst support functions adds 820e0bb9ce target/arm: Move expand_pred_b to vec_internal.h adds 05dd14bdfa target/arm: Use expand_pred_b in mve_helper.c adds a613cf2d4a target/arm: Move expand_pred_h to vec_internal.h adds 72db2aa353 target/arm: Export bfdotadd from vec_helper.c adds f305bf9436 target/arm: Add isar_feature_aa64_sme adds 414c54d515 target/arm: Add ID_AA64SMFR0_EL1 adds 028f2361d0 Merge tag 'pull-target-arm-20220609' of https://git.linaro.o [...] adds 7851b21a81 hw/ide/piix: Remove redundant "piix3-ide-xen" device class adds 3690241746 hw/ide/piix: Add some documentation to pci_piix3_xen_ide_unplug() adds 6a8a8b62bd include/hw/ide: Unexport pci_piix3_xen_ide_unplug() adds 9cc1bf1ebc Merge tag 'pull-xen-20220609' of https://xenbits.xen.org/git [...] adds efe1592c43 MAINTAINERS: Cover hw/core/uboot_image.h within Generic Load [...] adds de799beba7 target/riscv: add support for zmmul extension v0.1 adds f9a461b2d3 hw/riscv: virt: Generate fw_cfg DT node correctly adds 40244040a7 hw/intc: sifive_plic: Avoid overflowing the addr_config buffer adds af9751316e hw/core/loader: return image sizes as ssize_t adds 8f42415fc1 target/riscv: Wake on VS-level external interrupts adds d1d8541217 target/riscv/debug.c: keep experimental rv128 support working adds 8a085fb2ad target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed adds 25eae0486d target/riscv: rvv: Prune redundant access_type parameter passed adds c7b8a4213b target/riscv: rvv: Rename ambiguous esz adds 41d3d7f76a target/riscv: rvv: Early exit when vstart >= vl adds f1eed927fb target/riscv: rvv: Add tail agnostic for vv instructions adds 752614cab8 target/riscv: rvv: Add tail agnostic for vector load / store [...] adds 5c19fc156e target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions adds 7b1bff41c1 target/riscv: rvv: Add tail agnostic for vector integer shif [...] adds 38581e5c9a target/riscv: rvv: Add tail agnostic for vector integer comp [...] adds 89a32de2d5 target/riscv: rvv: Add tail agnostic for vector integer merg [...] adds 09106eed30 target/riscv: rvv: Add tail agnostic for vector fix-point ar [...] adds 5eacf7d8a0 target/riscv: rvv: Add tail agnostic for vector floating-poi [...] adds df4f52a758 target/riscv: rvv: Add tail agnostic for vector reduction in [...] adds acc6ffd482 target/riscv: rvv: Add tail agnostic for vector mask instructions adds 803963f7cb target/riscv: rvv: Add tail agnostic for vector permutation [...] adds b8312675d6 target/riscv: rvv: Add option 'rvv_ta_all_1s' to enable opti [...] adds 26b2bc5859 target/riscv: Don't expose the CPU properties on names CPUs adds 07314158f6 target/riscv: trans_rvv: Avoid assert for RV32 and e64 adds b3cd3b5a66 Merge tag 'pull-riscv-to-apply-20220610' of github.com:alist [...] adds 7666a81d15 target/arm: Mark exception helpers as noreturn adds fa33eead86 target/arm: Add coproc parameter to syn_fp_access_trap adds 57287a6e95 target/arm: Move exception_target_el out of line adds 55ba15b737 target/arm: Move arm_singlestep_active out of line adds 31c8df53ee target/arm: Move arm_generate_debug_exceptions out of line adds 831c1b1087 target/arm: Use is_a64 in arm_generate_debug_exceptions adds 16f9d5f693 target/arm: Move exception_bkpt_insn to debug_helper.c adds a853e3ae55 target/arm: Move arm_debug_exception_fsr to debug_helper.c adds d3c5d50a5c target/arm: Rename helper_exception_with_syndrome adds 9c9d03f0c5 target/arm: Introduce gen_exception_insn_el_v adds 8c5d24dc7d target/arm: Rename gen_exception_insn to gen_exception_insn_el adds 486d6c9699 target/arm: Introduce gen_exception_insn adds f0d7c2054a target/arm: Create helper_exception_swstep adds 8480e933ed target/arm: Remove TBFLAG_ANY.DEBUG_TARGET_EL adds cc5e672b85 target/arm: Move gen_exception to translate.c adds bca6f24f01 target/arm: Rename gen_exception to gen_exception_el adds 1a13b9a863 target/arm: Introduce gen_exception adds d6d7f818a9 target/arm: Introduce gen_exception_el_v adds eeaf596022 target/arm: Introduce helper_exception_with_syndrome adds 82303761c6 target/arm: Remove default_exception_el adds 04eacf6e79 target/arm: Create raise_exception_debug adds 38e8a13c11 target/arm: Move arm_debug_target_el to debug_helper.c adds 02e1de14bc target/arm: Fix Secure PL1 tests in fp_exception_el adds 284ad5e70c tests/qtest: Reduce npcm7xx_sdhci test image size adds bfe43e3d14 target/arm: Adjust format test in scr_write adds 6bcbb07af6 target/arm: SCR_EL3.RW is RAO/WI without AArch32 EL[12] adds ebf1b4cbb8 gdbstub: Don't use GDB syscalls if no GDB is attached adds 90c072e063 semihosting/config: Merge --semihosting-config option groups adds 2663c41cfa Merge tag 'pull-target-arm-20220610' of https://git.linaro.o [...]
No new revisions were added by this update.
Summary of changes: MAINTAINERS | 1 + accel/hvf/hvf-accel-ops.c | 4 +- accel/kvm/kvm-all.c | 4 +- accel/tcg/user-exec.c | 6 +- docs/interop/vhost-user.rst | 2 +- docs/specs/vmgenid.txt | 4 +- docs/system/arm/emulation.rst | 2 + gdbstub.c | 14 +- hw/acpi/ghes.c | 2 +- hw/arm/armv7m.c | 2 +- hw/arm/boot.c | 8 +- hw/arm/xlnx-zynqmp.c | 4 +- hw/core/generic-loader.c | 2 +- hw/core/loader.c | 81 +- hw/display/xlnx_dp.c | 49 +- hw/i386/pc_piix.c | 3 +- hw/i386/x86.c | 2 +- hw/i386/xen/xen_platform.c | 48 +- hw/ide/piix.c | 42 - hw/intc/arm_gicv3_cpuif.c | 2 +- hw/intc/arm_gicv3_dist.c | 2 +- hw/intc/arm_gicv3_redist.c | 4 +- hw/intc/riscv_aclint.c | 2 +- hw/intc/riscv_aplic.c | 2 +- hw/intc/sifive_plic.c | 19 +- hw/pci/shpc.c | 2 +- hw/riscv/boot.c | 5 +- hw/riscv/virt.c | 28 +- hw/scsi/mfi.h | 2 +- hw/sparc64/sun4u_iommu.c | 2 +- hw/timer/sse-timer.c | 2 +- hw/tpm/tpm_crb.c | 1 + hw/tpm/tpm_tis_common.c | 7 +- hw/vfio/common.c | 10 +- hw/vfio/trace-events | 2 +- include/hw/display/xlnx_dp.h | 12 +- include/hw/ide.h | 3 - include/hw/loader.h | 55 +- linux-user/aarch64/signal.c | 4 +- linux-user/aarch64/target_prctl.h | 18 +- python/qemu/machine/machine.py | 2 +- semihosting/config.c | 1 + target/arm/arch_dump.c | 2 +- target/arm/cpu.c | 5 +- target/arm/cpu.h | 199 +- target/arm/cpu64.c | 120 +- target/arm/debug_helper.c | 220 ++- target/arm/gdbstub.c | 2 +- target/arm/gdbstub64.c | 2 +- target/arm/helper.c | 3095 +++---------------------------- target/arm/helper.h | 8 +- target/arm/hvf/hvf.c | 4 +- target/arm/internals.h | 86 +- target/arm/kvm64.c | 47 +- target/arm/kvm_arm.h | 7 +- target/arm/meson.build | 1 + target/arm/mve_helper.c | 6 +- target/arm/op_helper.c | 52 +- target/arm/ptw.c | 2540 +++++++++++++++++++++++++ target/arm/sve_helper.c | 232 +-- target/arm/sve_ldst_internal.h | 221 +++ target/arm/syndrome.h | 7 +- target/arm/tlb_helper.c | 26 + target/arm/translate-a64.c | 36 +- target/arm/translate-a64.h | 2 +- target/arm/translate-m-nocp.c | 15 +- target/arm/translate-mve.c | 3 +- target/arm/translate-sve.c | 2 +- target/arm/translate-vfp.c | 18 +- target/arm/translate.c | 106 +- target/arm/translate.h | 45 +- target/arm/vec_helper.c | 28 +- target/arm/vec_internal.h | 28 +- target/i386/cpu-sysemu.c | 2 +- target/i386/hvf/vmcs.h | 2 +- target/i386/hvf/vmx.h | 2 +- target/riscv/cpu.c | 68 +- target/riscv/cpu.h | 4 + target/riscv/cpu_helper.c | 4 +- target/riscv/debug.c | 2 + target/riscv/insn_trans/trans_rvm.c.inc | 18 +- target/riscv/insn_trans/trans_rvv.c.inc | 106 +- target/riscv/internals.h | 6 +- target/riscv/translate.c | 4 + target/riscv/vector_helper.c | 1588 +++++++++------- target/s390x/ioinst.c | 2 +- tests/qtest/npcm7xx_sdhci-test.c | 2 +- tests/tcg/x86_64/system/boot.S | 2 +- 88 files changed, 5087 insertions(+), 4357 deletions(-) create mode 100644 target/arm/ptw.c create mode 100644 target/arm/sve_ldst_internal.h