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unknown user pushed a change to branch master in repository gcc.
from 33203b4c27d [ARM][GCC][4/2x]: MVE intrinsics with binary operands. new f9355dee93f [ARM][GCC][5/2x]: MVE intrinsics with binary operands.
The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.
Summary of changes: gcc/ChangeLog | 488 +++ gcc/config/arm/arm_mve.h | 3279 ++++++++++++++++---- gcc/config/arm/arm_mve_builtins.def | 468 +-- gcc/config/arm/mve.md | 1008 +++++- gcc/testsuite/ChangeLog | 150 + .../gcc.target/arm/mve/intrinsics/vabdq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabdq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c | 22 + .../intrinsics/{vsubq_n_f16.c => vaddq_n_f16.c} | 8 +- .../intrinsics/{vsubq_n_f32.c => vaddq_n_f32.c} | 8 +- .../intrinsics/{vcvtq_n_f16_s16.c => vandq_f16.c} | 12 +- .../intrinsics/{vcvtq_n_f32_s32.c => vandq_f32.c} | 12 +- .../intrinsics/{vcvtq_n_f16_s16.c => vbicq_f16.c} | 12 +- .../intrinsics/{vcvtq_n_f32_s32.c => vbicq_f32.c} | 12 +- .../intrinsics/{vmvnq_n_s16.c => vbicq_n_s16.c} | 6 +- .../intrinsics/{vmvnq_n_s32.c => vbicq_n_s32.c} | 6 +- .../intrinsics/{vdupq_n_u16.c => vbicq_n_u16.c} | 6 +- .../intrinsics/{vdupq_n_u32.c => vbicq_n_u32.c} | 6 +- .../arm/mve/intrinsics/vcaddq_rot270_f16.c | 22 + .../arm/mve/intrinsics/vcaddq_rot270_f32.c | 22 + .../arm/mve/intrinsics/vcaddq_rot90_f16.c | 22 + .../arm/mve/intrinsics/vcaddq_rot90_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c | 22 + .../intrinsics/{vsubq_n_f16.c => vcmpeqq_n_f16.c} | 12 +- .../intrinsics/{vsubq_n_f32.c => vcmpeqq_n_f32.c} | 12 +- .../gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c | 22 + .../intrinsics/{vsubq_n_f16.c => vcmpgeq_n_f16.c} | 12 +- .../intrinsics/{vsubq_n_f32.c => vcmpgeq_n_f32.c} | 12 +- .../gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c | 22 + .../intrinsics/{vsubq_n_f16.c => vcmpgtq_n_f16.c} | 12 +- .../intrinsics/{vsubq_n_f32.c => vcmpgtq_n_f32.c} | 12 +- .../gcc.target/arm/mve/intrinsics/vcmpleq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpleq_f32.c | 22 + .../intrinsics/{vsubq_n_f16.c => vcmpleq_n_f16.c} | 12 +- .../intrinsics/{vsubq_n_f32.c => vcmpleq_n_f32.c} | 12 +- .../gcc.target/arm/mve/intrinsics/vcmpltq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpltq_f32.c | 22 + .../intrinsics/{vsubq_n_f16.c => vcmpltq_n_f16.c} | 12 +- .../intrinsics/{vsubq_n_f32.c => vcmpltq_n_f32.c} | 12 +- .../gcc.target/arm/mve/intrinsics/vcmpneq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_f32.c | 22 + .../intrinsics/{vsubq_n_f16.c => vcmpneq_n_f16.c} | 12 +- .../intrinsics/{vsubq_n_f32.c => vcmpneq_n_f32.c} | 12 +- .../gcc.target/arm/mve/intrinsics/vcmulq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmulq_f32.c | 22 + .../arm/mve/intrinsics/vcmulq_rot180_f16.c | 22 + .../arm/mve/intrinsics/vcmulq_rot180_f32.c | 22 + .../arm/mve/intrinsics/vcmulq_rot270_f16.c | 22 + .../arm/mve/intrinsics/vcmulq_rot270_f32.c | 22 + .../arm/mve/intrinsics/vcmulq_rot90_f16.c | 22 + .../arm/mve/intrinsics/vcmulq_rot90_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vctp16q_m.c | 23 + .../gcc.target/arm/mve/intrinsics/vctp32q_m.c | 23 + .../gcc.target/arm/mve/intrinsics/vctp64q_m.c | 23 + .../gcc.target/arm/mve/intrinsics/vctp8q_m.c | 23 + .../intrinsics/{vabsq_f16.c => vcvtbq_f16_f32.c} | 6 +- .../intrinsics/{vabsq_f16.c => vcvttq_f16_f32.c} | 6 +- .../intrinsics/{vcvtq_n_f16_s16.c => veorq_f16.c} | 12 +- .../intrinsics/{vcvtq_n_f32_s32.c => veorq_f32.c} | 12 +- .../gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c | 2 +- .../gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c | 2 +- .../gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c | 2 +- .../gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c | 2 +- .../gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmaq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmaq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmavq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmavq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmvq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmvq_f32.c | 22 + .../intrinsics/{vabdq_s16.c => vmlaldavq_s16.c} | 12 +- .../intrinsics/{vcmpeqq_s32.c => vmlaldavq_s32.c} | 12 +- .../intrinsics/{vbicq_u16.c => vmlaldavq_u16.c} | 12 +- .../intrinsics/{vabdq_u32.c => vmlaldavq_u32.c} | 12 +- .../{vcaddq_rot90_s16.c => vmlaldavxq_s16.c} | 12 +- .../{vcaddq_rot90_s32.c => vmlaldavxq_s32.c} | 12 +- .../intrinsics/{vcmpeqq_s16.c => vmlsldavq_s16.c} | 12 +- .../intrinsics/{vcmpeqq_s32.c => vmlsldavq_s32.c} | 12 +- .../{vcaddq_rot90_s16.c => vmlsldavxq_s16.c} | 12 +- .../{vcaddq_rot90_s32.c => vmlsldavxq_s32.c} | 12 +- .../gcc.target/arm/mve/intrinsics/vmovnbq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovnbq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovnbq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovnbq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovntq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovntq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovntq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovntq_u32.c | 22 + .../{vmullbq_int_u16.c => vmullbq_poly_p16.c} | 8 +- .../{vmullbq_int_u8.c => vmullbq_poly_p8.c} | 8 +- .../{vmullbq_int_u16.c => vmulltq_poly_p16.c} | 8 +- .../{vmullbq_int_u8.c => vmulltq_poly_p8.c} | 8 +- .../gcc.target/arm/mve/intrinsics/vmulq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_f32.c | 22 + .../intrinsics/{vsubq_n_f16.c => vmulq_n_f16.c} | 8 +- .../intrinsics/{vsubq_n_f32.c => vmulq_n_f32.c} | 8 +- .../intrinsics/{vcvtq_n_f16_s16.c => vornq_f16.c} | 12 +- .../intrinsics/{vcvtq_n_f32_s32.c => vornq_f32.c} | 12 +- .../intrinsics/{vcvtq_n_f16_s16.c => vorrq_f16.c} | 12 +- .../intrinsics/{vcvtq_n_f32_s32.c => vorrq_f32.c} | 12 +- .../intrinsics/{vmvnq_n_s16.c => vorrq_n_s16.c} | 6 +- .../intrinsics/{vmvnq_n_s32.c => vorrq_n_s32.c} | 6 +- .../intrinsics/{vdupq_n_u16.c => vorrq_n_u16.c} | 6 +- .../intrinsics/{vdupq_n_u32.c => vorrq_n_u32.c} | 6 +- .../gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c | 2 +- .../{vaddq_n_s16.c => vqdmullbq_n_s16.c} | 12 +- .../{vbrsrq_n_s32.c => vqdmullbq_n_s32.c} | 12 +- .../{vmullbq_int_s16.c => vqdmullbq_s16.c} | 8 +- .../{vmullbq_int_s32.c => vqdmullbq_s32.c} | 8 +- .../{vaddq_n_s16.c => vqdmulltq_n_s16.c} | 12 +- .../{vbrsrq_n_s32.c => vqdmulltq_n_s32.c} | 12 +- .../{vmullbq_int_s16.c => vqdmulltq_s16.c} | 8 +- .../{vmullbq_int_s32.c => vqdmulltq_s32.c} | 8 +- .../gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovntq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovntq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovntq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovntq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c | 22 + .../arm/mve/intrinsics/vqrdmulhq_n_s16.c | 2 +- .../arm/mve/intrinsics/vqrdmulhq_n_s32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c | 2 +- .../{vcaddq_rot270_s32.c => vrmlaldavhq_s32.c} | 12 +- .../intrinsics/{vabdq_u32.c => vrmlaldavhq_u32.c} | 12 +- .../{vcaddq_rot270_s32.c => vrmlaldavhxq_s32.c} | 12 +- .../{vcaddq_rot270_s32.c => vrmlsldavhq_s32.c} | 12 +- .../intrinsics/{vabdq_s32.c => vrmlsldavhxq_s32.c} | 12 +- .../gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c | 2 +- .../gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c | 2 +- .../gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c | 2 +- .../gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c | 2 +- .../intrinsics/{vrev64q_s16.c => vshllbq_n_s16.c} | 12 +- .../intrinsics/{vmovltq_s8.c => vshllbq_n_s8.c} | 8 +- .../intrinsics/{vmovltq_u16.c => vshllbq_n_u16.c} | 8 +- .../intrinsics/{vmovltq_u8.c => vshllbq_n_u8.c} | 8 +- .../intrinsics/{vrev64q_s16.c => vshlltq_n_s16.c} | 12 +- .../intrinsics/{vmovltq_s8.c => vshlltq_n_s8.c} | 8 +- .../intrinsics/{vmovltq_u16.c => vshlltq_n_u16.c} | 8 +- .../intrinsics/{vmovltq_u8.c => vshlltq_n_u8.c} | 8 +- .../mve/intrinsics/{vsubq_n_f16.c => vsubq_f16.c} | 6 +- .../mve/intrinsics/{vsubq_n_f32.c => vsubq_f32.c} | 6 +- .../gcc.target/arm/mve/intrinsics/vsubq_n_s16.c | 3 +- .../gcc.target/arm/mve/intrinsics/vsubq_n_s32.c | 3 +- .../gcc.target/arm/mve/intrinsics/vsubq_n_s8.c | 3 +- .../gcc.target/arm/mve/intrinsics/vsubq_n_u16.c | 3 +- .../gcc.target/arm/mve/intrinsics/vsubq_n_u32.c | 3 +- .../gcc.target/arm/mve/intrinsics/vsubq_n_u8.c | 3 +- 205 files changed, 6531 insertions(+), 1258 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_n_f16.c => vaddq_n_f16.c} (65%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_n_f32.c => vaddq_n_f32.c} (65%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_n_f16_s16.c => vandq_f16.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_n_f32_s32.c => vandq_f32.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_n_f16_s16.c => vbicq_f16.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_n_f32_s32.c => vbicq_f32.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmvnq_n_s16.c => vbicq_n_s16.c} (66%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmvnq_n_s32.c => vbicq_n_s32.c} (66%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdupq_n_u16.c => vbicq_n_u16.c} (66%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdupq_n_u32.c => vbicq_n_u32.c} (66%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_n_f16.c => vcmpeqq_n_f16.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_n_f32.c => vcmpeqq_n_f32.c} (58%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_n_f16.c => vcmpgeq_n_f16.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_n_f32.c => vcmpgeq_n_f32.c} (58%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_n_f16.c => vcmpgtq_n_f16.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_n_f32.c => vcmpgtq_n_f32.c} (58%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f32.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_n_f16.c => vcmpleq_n_f16.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_n_f32.c => vcmpleq_n_f32.c} (58%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f32.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_n_f16.c => vcmpltq_n_f16.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_n_f32.c => vcmpltq_n_f32.c} (58%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f32.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_n_f16.c => vcmpneq_n_f16.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_n_f32.c => vcmpneq_n_f32.c} (58%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q_m.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q_m.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q_m.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q_m.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabsq_f16.c => vcvtbq_f16_f32.c} (62%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabsq_f16.c => vcvttq_f16_f32.c} (62%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_n_f16_s16.c => veorq_f16.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_n_f32_s32.c => veorq_f32.c} (50%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabdq_s16.c => vmlaldavq_s16.c} (57%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpeqq_s32.c => vmlaldavq_s32.c} (57%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_u16.c => vmlaldavq_u16.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabdq_u32.c => vmlaldavq_u32.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcaddq_rot90_s16.c => vmlaldavxq [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcaddq_rot90_s32.c => vmlaldavxq [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpeqq_s16.c => vmlsldavq_s16.c} (57%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpeqq_s32.c => vmlsldavq_s32.c} (57%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcaddq_rot90_s16.c => vmlsldavxq [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcaddq_rot90_s32.c => vmlsldavxq [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u32.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmullbq_int_u16.c => vmullbq_pol [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmullbq_int_u8.c => vmullbq_poly [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmullbq_int_u16.c => vmulltq_pol [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmullbq_int_u8.c => vmulltq_poly [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f32.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_n_f16.c => vmulq_n_f16.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_n_f32.c => vmulq_n_f32.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_n_f16_s16.c => vornq_f16.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_n_f32_s32.c => vornq_f32.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_n_f16_s16.c => vorrq_f16.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_n_f32_s32.c => vorrq_f32.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmvnq_n_s16.c => vorrq_n_s16.c} (66%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmvnq_n_s32.c => vorrq_n_s32.c} (66%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdupq_n_u16.c => vorrq_n_u16.c} (66%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdupq_n_u32.c => vorrq_n_u32.c} (66%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vaddq_n_s16.c => vqdmullbq_n_s16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbrsrq_n_s32.c => vqdmullbq_n_s3 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmullbq_int_s16.c => vqdmullbq_s [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmullbq_int_s32.c => vqdmullbq_s [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vaddq_n_s16.c => vqdmulltq_n_s16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbrsrq_n_s32.c => vqdmulltq_n_s3 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmullbq_int_s16.c => vqdmulltq_s [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmullbq_int_s32.c => vqdmulltq_s [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcaddq_rot270_s32.c => vrmlaldav [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabdq_u32.c => vrmlaldavhq_u32.c} (57%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcaddq_rot270_s32.c => vrmlaldav [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcaddq_rot270_s32.c => vrmlsldav [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabdq_s32.c => vrmlsldavhxq_s32. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vrev64q_s16.c => vshllbq_n_s16.c} (55%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovltq_s8.c => vshllbq_n_s8.c} (60%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovltq_u16.c => vshllbq_n_u16.c} (60%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovltq_u8.c => vshllbq_n_u8.c} (61%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vrev64q_s16.c => vshlltq_n_s16.c} (55%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovltq_s8.c => vshlltq_n_s8.c} (60%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovltq_u16.c => vshlltq_n_u16.c} (60%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovltq_u8.c => vshlltq_n_u8.c} (61%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_n_f16.c => vsubq_f16.c} (77%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_n_f32.c => vsubq_f32.c} (77%)