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from 0a8dc0861b8 AMDGPU: Fix SMEM WAR hazard for gfx10 readlane new 90696971b2a [examples] Add an example of how to use JITLink and small-c [...] new 7d97468a231 AMDGPU: Relax 32-bit SGPR register class
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Summary of changes: examples/LLJITExamples/CMakeLists.txt | 1 + .../CMakeLists.txt | 4 +- .../LLJITWithJITLink/LLJITWithJITLink.cpp | 70 ++++++ lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 2 +- lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp | 17 +- lib/Target/AMDGPU/SIISelLowering.cpp | 32 +-- lib/Target/AMDGPU/SIInstrInfo.cpp | 8 +- lib/Target/AMDGPU/SIRegisterInfo.cpp | 12 +- lib/Target/AMDGPU/SIRegisterInfo.h | 2 +- test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir | 4 +- .../AMDGPU/GlobalISel/inst-select-amdgcn.class.mir | 24 +- .../GlobalISel/inst-select-amdgcn.class.s16.mir | 14 +- .../AMDGPU/GlobalISel/inst-select-amdgcn.cos.mir | 2 +- .../GlobalISel/inst-select-amdgcn.cos.s16.mir | 2 +- .../GlobalISel/inst-select-amdgcn.cvt.pk.i16.mir | 4 +- .../GlobalISel/inst-select-amdgcn.cvt.pk.u16.mir | 4 +- .../inst-select-amdgcn.cvt.pknorm.i16.mir | 4 +- .../inst-select-amdgcn.cvt.pknorm.u16.mir | 4 +- .../GlobalISel/inst-select-amdgcn.cvt.pkrtz.mir | 4 +- .../AMDGPU/GlobalISel/inst-select-amdgcn.fmed3.mir | 14 +- .../GlobalISel/inst-select-amdgcn.fmed3.s16.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-amdgcn.fract.mir | 2 +- .../GlobalISel/inst-select-amdgcn.fract.s16.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-amdgcn.ldexp.mir | 6 +- .../GlobalISel/inst-select-amdgcn.ldexp.s16.mir | 4 +- .../GlobalISel/inst-select-amdgcn.mbcnt.lo.mir | 4 +- .../GlobalISel/inst-select-amdgcn.rcp.legacy.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-amdgcn.rcp.mir | 2 +- .../GlobalISel/inst-select-amdgcn.rcp.s16.mir | 2 +- .../GlobalISel/inst-select-amdgcn.rsq.clamp.mir | 2 +- .../GlobalISel/inst-select-amdgcn.rsq.legacy.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-amdgcn.rsq.mir | 2 +- .../GlobalISel/inst-select-amdgcn.rsq.s16.mir | 2 +- .../GlobalISel/inst-select-amdgcn.s.sendmsg.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-amdgcn.sffbh.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-amdgcn.sin.mir | 2 +- .../GlobalISel/inst-select-amdgcn.sin.s16.mir | 2 +- .../GlobalISel/inst-select-amdgpu-ffbh-u32.mir | 2 +- test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir | 66 +++--- .../AMDGPU/GlobalISel/inst-select-anyext.mir | 12 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mir | 30 +-- .../AMDGPU/GlobalISel/inst-select-ashr.s16.mir | 12 +- .../AMDGPU/GlobalISel/inst-select-bitreverse.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-brcond.mir | 8 +- .../AMDGPU/GlobalISel/inst-select-build-vector.mir | 16 +- .../GlobalISel/inst-select-concat-vectors.mir | 32 +-- .../AMDGPU/GlobalISel/inst-select-constant.mir | 8 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir | 26 +-- .../AMDGPU/GlobalISel/inst-select-ctpop.mir | 8 +- .../AMDGPU/GlobalISel/inst-select-extract.mir | 96 ++++---- .../CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir | 8 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.mir | 56 ++--- .../AMDGPU/GlobalISel/inst-select-fcmp.s16.mir | 28 +-- .../AMDGPU/GlobalISel/inst-select-ffloor.mir | 4 +- .../AMDGPU/GlobalISel/inst-select-ffloor.s16.mir | 6 +- .../AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.mir | 4 +- .../AMDGPU/GlobalISel/inst-select-fmaxnum.mir | 4 +- .../AMDGPU/GlobalISel/inst-select-fminnum-ieee.mir | 4 +- .../AMDGPU/GlobalISel/inst-select-fminnum.mir | 4 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir | 4 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir | 20 +- .../AMDGPU/GlobalISel/inst-select-fptosi.mir | 4 +- .../AMDGPU/GlobalISel/inst-select-fptoui.mir | 4 +- .../AMDGPU/GlobalISel/inst-select-frame-index.mir | 2 +- test/CodeGen/AMDGPU/GlobalISel/inst-select-gep.mir | 10 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-icmp.mir | 10 +- .../AMDGPU/GlobalISel/inst-select-implicit-def.mir | 6 +- .../AMDGPU/GlobalISel/inst-select-insert.mir | 8 +- .../GlobalISel/inst-select-load-constant.mir | 16 +- .../AMDGPU/GlobalISel/inst-select-load-smrd.mir | 20 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-lshr.mir | 30 +-- .../AMDGPU/GlobalISel/inst-select-lshr.s16.mir | 12 +- .../AMDGPU/GlobalISel/inst-select-merge-values.mir | 40 ++-- test/CodeGen/AMDGPU/GlobalISel/inst-select-mul.mir | 4 +- test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir | 66 +++--- test/CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir | 92 ++++++-- .../AMDGPU/GlobalISel/inst-select-ptr-mask.mir | 22 +- .../AMDGPU/GlobalISel/inst-select-ptrtoint.mir | 4 +- .../AMDGPU/GlobalISel/inst-select-select.mir | 12 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir | 18 +- test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.mir | 30 +-- .../AMDGPU/GlobalISel/inst-select-shl.s16.mir | 12 +- .../AMDGPU/GlobalISel/inst-select-sitofp.mir | 16 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-smax.mir | 4 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-smin.mir | 4 +- .../AMDGPU/GlobalISel/inst-select-smulh.mir | 4 +- test/CodeGen/AMDGPU/GlobalISel/inst-select-sub.mir | 6 +- .../AMDGPU/GlobalISel/inst-select-trunc.mir | 14 +- .../AMDGPU/GlobalISel/inst-select-uaddo.mir | 24 +- .../AMDGPU/GlobalISel/inst-select-uitofp.mir | 16 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-umax.mir | 4 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-umin.mir | 4 +- .../AMDGPU/GlobalISel/inst-select-umulh.mir | 4 +- .../GlobalISel/inst-select-unmerge-values.mir | 24 +- .../AMDGPU/GlobalISel/inst-select-usubo.mir | 24 +- test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir | 66 +++--- .../CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir | 18 +- .../llvm.amdgcn.raw.buffer.store.format.f16.ll | 176 +++++++-------- .../llvm.amdgcn.raw.buffer.store.format.f32.ll | 88 ++++---- .../GlobalISel/llvm.amdgcn.raw.buffer.store.ll | 242 ++++++++++----------- .../AMDGPU/buffer-intrinsics-mmo-offsets.ll | 46 ++-- test/CodeGen/AMDGPU/extract_subvector_vec4_vec3.ll | 7 +- test/CodeGen/AMDGPU/inline-constraints.ll | 5 +- test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll | 4 +- test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll | 3 +- test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll | 4 +- test/CodeGen/AMDGPU/read_register.ll | 4 +- 107 files changed, 1047 insertions(+), 916 deletions(-) copy examples/LLJITExamples/{LLJITWithObjectCache => LLJITWithJITLink}/CMakeLists. [...] create mode 100644 examples/LLJITExamples/LLJITWithJITLink/LLJITWithJITLink.cpp