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from d91a0cee361 [PATCH] RISC-V: Add XiangShan Nanhu microarchitecture. new 9eeca775367 [PATCH v5 1/1] RISC-V: Add support for XCVbi extension in CV32E40P
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Summary of changes: gcc/common/config/riscv/riscv-common.cc | 2 + gcc/config/riscv/constraints.md | 6 +++ gcc/config/riscv/corev.md | 37 +++++++++++++++++ gcc/config/riscv/predicates.md | 4 ++ gcc/config/riscv/riscv.md | 2 +- gcc/config/riscv/riscv.opt | 2 + gcc/doc/sourcebuild.texi | 3 ++ .../gcc.target/riscv/cv-bi-beqimm-compile-1.c | 17 ++++++++ .../gcc.target/riscv/cv-bi-beqimm-compile-2.c | 48 ++++++++++++++++++++++ .../gcc.target/riscv/cv-bi-bneimm-compile-1.c | 17 ++++++++ .../gcc.target/riscv/cv-bi-bneimm-compile-2.c | 48 ++++++++++++++++++++++ gcc/testsuite/lib/target-supports.exp | 13 ++++++ 12 files changed, 198 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c