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from 6eae3d18ede [CUDA] updated CompileCudaWithLLVM.rst new 322a8075ef7 [AMDGPU] Add FixupVectorISel pass, currently Supports SREGs [...] new f8ecfaae822 [VFS] Implement `RedirectingFileSystem::getRealPath`. new 9193df0c9dc [X86] Update a couple comments to remove a mention of a sig [...] new 46c010779c2 [X86] Use ANY_EXTEND instead of SIGN_EXTEND in the AVX2 and [...]
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Summary of changes: lib/Support/VirtualFileSystem.cpp | 33 +- lib/Target/AMDGPU/AMDGPU.h | 4 + lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 2 + lib/Target/AMDGPU/CMakeLists.txt | 1 + lib/Target/AMDGPU/FLATInstructions.td | 23 +- lib/Target/AMDGPU/SIFixupVectorISel.cpp | 224 ++++++ lib/Target/AMDGPU/SIInstrInfo.h | 3 + lib/Target/AMDGPU/SIInstrInfo.td | 9 + lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 1 + lib/Target/X86/X86ISelLowering.cpp | 10 +- test/CodeGen/AMDGPU/ds_write2.ll | 12 +- test/CodeGen/AMDGPU/ds_write2st64.ll | 12 +- test/CodeGen/AMDGPU/global-load-store-atomics.mir | 249 ++++++ test/CodeGen/AMDGPU/global-saddr.ll | 102 +++ test/CodeGen/AMDGPU/indirect-addressing-si-gfx9.ll | 85 +++ .../AMDGPU/indirect-addressing-si-pregfx9.ll | 88 +++ test/CodeGen/AMDGPU/indirect-addressing-si.ll | 73 +- test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll | 32 +- .../insert_vector_elt.v2i16.subtest-nosaddr.ll | 36 + .../insert_vector_elt.v2i16.subtest-saddr.ll | 36 + test/CodeGen/AMDGPU/madak.ll | 12 +- test/CodeGen/AMDGPU/memory-legalizer-load.ll | 2 +- test/CodeGen/AMDGPU/memory-legalizer-store.ll | 2 +- test/CodeGen/AMDGPU/memory_clause.ll | 2 +- test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll | 15 +- test/CodeGen/X86/avx2-arith.ll | 24 +- test/CodeGen/X86/combine-mul.ll | 2 +- test/CodeGen/X86/pmul.ll | 108 +-- test/CodeGen/X86/vector-mul.ll | 6 +- test/CodeGen/X86/vector-reduce-mul.ll | 832 +++++++++------------ test/CodeGen/X86/vector-shift-shl-128.ll | 2 +- unittests/Support/VirtualFileSystemTest.cpp | 46 ++ 32 files changed, 1401 insertions(+), 687 deletions(-) create mode 100644 lib/Target/AMDGPU/SIFixupVectorISel.cpp create mode 100644 test/CodeGen/AMDGPU/global-load-store-atomics.mir create mode 100644 test/CodeGen/AMDGPU/global-saddr.ll create mode 100644 test/CodeGen/AMDGPU/indirect-addressing-si-gfx9.ll create mode 100644 test/CodeGen/AMDGPU/indirect-addressing-si-pregfx9.ll create mode 100644 test/CodeGen/AMDGPU/insert_vector_elt.v2i16.subtest-nosaddr.ll create mode 100644 test/CodeGen/AMDGPU/insert_vector_elt.v2i16.subtest-saddr.ll