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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_check/master-aarch64 in repository toolchain/ci/gcc.
from 34afa19d29c fold-const: do not fold NaN result from non-NaN operands [PR95115] adds b9ebf6c330e PR101260 regcprop: Add mode change check for copy reg adds 7e836079071 rs6000: Don't #ifdef "short" built-in names adds e9bf6d6b0e1 veclower: Fix up -fcompare-debug issue in expand_vector_com [...] adds 3ad29854f0b docs: remove --disable-stage1-checking from requirements adds 07a971b28c8 Strengthen memory order for atomic<T>::wait/notify
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Summary of changes: gcc/config/rs6000/rs6000-overload.def | 344 ++++++++++++++++--------------- gcc/doc/install.texi | 5 - gcc/regcprop.cc | 3 +- gcc/testsuite/gcc.target/i386/pr104307.c | 6 + gcc/testsuite/gcc.target/s390/pr101260.c | 63 ++++++ gcc/tree-vect-generic.cc | 38 ++-- libstdc++-v3/include/bits/atomic_wait.h | 12 +- 7 files changed, 271 insertions(+), 200 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr104307.c create mode 100644 gcc/testsuite/gcc.target/s390/pr101260.c