[Tcwg-commits] [toolchain/llvm/llvm] branch linaro-local/thomas.preudhomme/llvm-432-rebase updated (5dc6d7ebade -> b55d31dd34d)

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thomas.preudhomme pushed a change to branch linaro-local/thomas.preudhomme/llvm-432-rebase in repository toolchain/llvm/llvm.

discards 5dc6d7ebade FileCheck: Add support for numeric variables and expressions discards 5684199be3f Detect incorrect FileCheck variable CLI definition adds a3836a558f3 [mir] Serialize DILocation inline when not possible to use [...] adds d7736b84c47 [SystemZ] Pass copy-hinted regs first from getRegAllocatio [...] adds 4a6ddb98afb [X86][SSE] Merge the vXi16/vXi32 vector rotation expansion [...] adds c8712c4ca0a [tblgen][disasm] Separate encodings from instructions adds a20dcc7643d [mir] Fix uninitialized variable in r349035 noticed by clan [...] adds 6250c9b5098 [PowerPC][NFC] Sorting out Pseudo related classes to avoid [...] adds cf52156a7d9 [Sparc] Use float register for integer constrained with "f" [...] adds 9dc429df9c4 Revert r349041: [tblgen][disasm] Separate encodings from in [...] adds 02083ba06c6 [X86][SSE] Fix modulo rotation amounts for v8i16/v16i16/v4i [...] adds 6c26f62b8b0 [Sparc] Add membar assembler tags adds aab76e7c51f [DAGCombiner] after simplifying demanded elements of vector [...] adds d2cb9435c71 [X86][SSE] Fix all remaining modulo vector rotation amounts [...] adds 0de7068d4e7 Recommit r349041: [tblgen][disasm] Separate encodings from [...] adds 82ad560a7e4 revert rL349051: [DAGCombiner] after simplifying demanded e [...] adds 77a2bc81a9b [X86][SSE] Add SSE vector imm/var shift support to Simplify [...] adds ad397e7b26b [DAGCombiner] after simplifying demanded elements of vector [...] adds 4e2709968cd [MachO][TLOF] Add support for local symbols in the indirect [...] adds 547b2b793df Correctly handle skewed streams in drop_front() method. adds befe7b1ade0 Don't add unnecessary compiler flags to llvm-config output adds 85d2ac25292 [LoopUtils] Use i32 instead of `void`. adds 1215e65a789 [CMake] llvm_codesign workaround for Xcode double-signing errors adds 4d8d496e939 [CostModel][X86] Don't count 2 shuffles on the last level o [...] adds 91c68851b70 [llvm-size][libobject] Add explicit "inTextSegment" methods [...] adds e08b71132a1 [llvm] Address base discriminator overflow in X86Discrimina [...] adds f1f1adc004a [ThinLTO] Compute synthetic function entry count adds 45be87d306a Reapply "[MemCpyOpt] memset->memcpy forwarding with undef tail" adds dfc96459648 AMDGPU/GlobalISel: Legalize/regbankselect block_addr adds cc31a27f1ef Revert r348971: [AMDGPU] Support for "uniform-work-group-si [...] adds acfb046e52c [SampleFDO] handle ProfileSampleAccurate when initializing [...] adds 55eb8feef89 [AArch64] Fix Exynos predicates (NFC) adds 9c11e2a771d Revert "[hwasan] Android: Switch from TLS_SLOT_TSAN(8) to T [...] adds 56a07a98f89 [X86] Demote EmitTest to a helper function of EmitCmp. Rout [...] adds 1b4867a8d93 [DAGCombiner] clean up visitEXTRACT_VECTOR_ELT adds 4a6dc2dde35 [gn build] Add infrastructure to create symlinks and use it [...] adds ee2b0072830 Silence CMP0048 warning in the benchmark utility library adds 6592c09789e [macho] save the SDK version stored in module metadata into [...] adds 0f4c901bc99 [llvm-xray] Support for PIE adds f4a9ec323e3 [gn build] Merge r348963 and r349076 adds 43a722e52d4 [llvm-xray] Store offset pointers in temporaries adds c8c5302c5bc [llvm-xray] Use correct variable name adds 4daae1f32d6 [Object] Rename getRelrRelocationType to getRelativeRelocationType adds 6ff010a6c21 [ThinLTO] Fix test added in rL349076 adds 97c14736286 [llvm-exegesis] Optimize ToProcess in dbScan adds 6d356c8850c [DAGCombiner][X86] Prevent visitSIGN_EXTEND from returning [...] adds a32130ae388 Revert rL349136: [llvm-exegesis] Optimize ToProcess in dbScan adds c25292edd5c [TableGen:AsmWriter] Cope with consecutive tied operands. adds f4f855ccc75 [ARM GlobalISel] Allow simple binary ops in Thumb2 adds 53a285d891c [ARM GlobalISel] Minor refactoring. NFCI adds bbcda06d822 [ARM GlobalISel] Remove duplicate test. NFCI adds 5e8ab563691 [ARM GlobalISel] Thumb2: casts between int and ptr adds 98689c01bbf [RegAllocGreedy] IMPLICIT_DEF values shouldn't prefer registers adds b9a4d1d36a5 Implement -frecord-command-line (-frecord-gcc-switches) adds 6fcb14e9a46 NFC. Adding an empty line to test the updated commit credentials. adds e5cda03ac45 [x86] make tests immune to scalarization improvements; NFC adds 29d34db322c [x86] regenerate test checks; NFC adds 0c4a33bebe9 [x86] auto-generate complete checks; NFC adds 3fcf2a43426 [Hexagon] make test immune to scalarization improvements; NFC adds 74af87e5079 [SystemZ] make test immune to scalarization improvements; NFC adds 2b3b9e148b4 Fix a crash in llvm-undname with invalid types. adds c0cd92909ef [AArch64] make test immune to scalarization improvements; NFC adds a9359267b4b [globalisel][combiner] Make the CombinerChangeObserver a Ma [...] adds dc7d02c770d [MS Demangler] Add a regression test for an invalid mangled name. adds d7f1cd2c3fe [MS Demangler] Fail gracefully on invalid pointer types. adds c681401eacc [Transforms] Preserve metadata when converting invoke to call. adds 00d521d2a05 Fix Visual Studio PointerIntPair visualizer adds 3a50d5b9126 [ADT] Fix bugs in SmallBitVector. adds 15e2a129d81 [globalisel][combiner] Fix r349167 for release mode bots adds dac6042d844 [x86] make tests immune to scalarization improvements; NFC adds b8a683696fe [ARM] make test immune to scalarization improvements; NFC adds 955eced56a3 [x86] add tests for extractelement of FP binops; NFC adds a5a1ebaef15 [TransformWarning] Do not warn missed transformations in op [...] adds f2511abd84e [AArch64] Simplify the scheduling predicates (NFC) adds cdc0cba7f3f [SDAG] Ignore chain operand in REG_SEQUENCE when emitting i [...] adds 56ea4893da5 Add missing includes and forward decls to unbreak build adds 0bbe50f2fb4 [AMDGPU] Promote constant offset to the immediate by findin [...] adds cba44d9b382 [Hexagon] Use IMPLICIT_DEF to any-extend 32-bit values to 64 bits adds 878b42a93b0 [GlobalISel] LegalizerHelper: Implement fewerElementsVector [...] adds af2984265a8 [Hexagon] Add patterns for shifts of v2i16 adds b2251b3e323 DebugInfo: Move addAddrBase from DwarfUnit to DwarfCompileUnit adds 3cc32f95a30 [codeview] Add begin/endSymbolRecord helpers, NFC adds b4b260e1797 DebugInfo: Avoid using split DWARF when the split unit woul [...] adds fb3de31920f [NVPTX] Lower instructions that expand into libcalls. adds 726751627e3 [Util] Refer to [s|z]exts of args when converting dbg.decla [...] adds e4bfa17a91e [NewGVN] Update use counts for SSA copies when replacing th [...] adds e2f3e50df6a [WebAssembly] Check if the section order is correct adds 7a4d0b9a104 [X86] Make hasNoCarryFlagUses/hasNoSignedComparisonUses tak [...] adds bf1554b9031 [X86] Rename hasNoSignedComparisonUses to hasNoSignFlagUses [...] adds c3c2387894d [SILoadStoreOptimizer] Use std::abs to avoid truncation. adds 1921566f91e [Power9][NFC] add setb exploitation test case adds c54b6d11d6b [mips] Fix test typo in rL348914 adds 7c45236930c [InstSimplify] Add tests for saturating add/sub + icmp; NFC adds 1fe1ffe00e0 [TargetLowering] Add ISD::OR + ISD::XOR handling to Simplif [...] adds cd3015238be Fix -Wunused-variable warning. NFCI. adds 75e4c6215f0 Regenerate neon copy tests. NFCI. adds b0f4bab2db1 [CodeGen] Enhance machine PHIs optimization adds 267dfed3ade Register kASan shadow offset for NetBSD/amd64 adds 50df229c26a Add NetBSD support in needsRuntimeRegistrationOfSectionRange. adds f7f12476f99 [X86] Add optsize SHLD/SHRD tests adds 0ef8b711371 [X86] Lower to SHLD/SHRD on slow machines for optsize adds f0db4e74b45 [X86] Begin cleaning up combineOr -> SHLD/SHRD. NFCI. adds 4ade6c45f2c [X86] Autogenerate complete checks. NFC adds 0c53afc25d2 [gn build] Add build files for llvm-as, llvm-dis, llvm-dwar [...] adds 6189ca00b18 [gn build] Add build files for obj2yaml, yaml2obj, and lib/ [...] adds 10cdfc9e777 [gn build] Merge r349167 adds 7f737c44006 [X86] Add computeKnownBits tests for funnel shift intrinsics adds c1aee892b9c [SelectionDAG] Add FSHL/FSHR support to computeKnownBits adds 6154b3404b1 Document the usage of BOOTSTRAP_XXX with stage2 builds adds c23bed32d43 Use backquotes to avoid a sphinx unexpected error: Unknown [...] adds e253500cfce Update the list of platforms & archs adds c5f4a842fff [DAGCombiner] allow hoisting vector bitwise logic ahead of [...] adds d353a688c4e [x86] increment/decrement constant vector with min/max in v [...] adds f96c9df4385 [InstCombine] add tests for vector widening transforms (PR4 [...] adds 421218c7405 [InstCombine] regenerate test checks; NFC adds dbb2df9229b [InstCombine] Add additional saturating add/sub + icmp tests; NFC adds ac6fe2834cb [InstCombined] Add more tests for cttz/ctlz + icmp; NFC adds 3937045b029 [InstCombine] Regenerate test checks; NFC adds 67f59bef66c Revert "[InstCombine] Regenerate test checks; NFC" adds af08be2c8a5 [X86] Autogenerate complete checks. NFC adds 53dfd27cfe8 [X86] Remove truncation handling from EmitTest. Replace it [...] adds 80a3a8cae42 Regenerate test (merges X86+X64 cases). NFCI. adds 96b0ff50830 [InstCombine] Make cttz/ctlz knownbits tests more robust; NFC adds 032b00a5404 [X86] Pull out constant splat rotation detection. adds 745ea2fc32a [InstCombine] Regenerate test checks; NFC adds 8f7655d1e44 [InstCombine] Add cttz/ctlz + select non-bitwidth tests; NFC adds 37676b50b62 [EarlyCSE] If DI can't be salvaged, mark it as unavailable. adds fae8aa36b36 [gn build] Add build files for opt and its dependency Trans [...] adds d279ef3f2d7 [Power9][NFC]Make pre-inc-disable case more robust adds 847f938b2ee [Power9][NFC]update vabsd case for better dumping adds 8f40271f0cb [X86] Fix bad operand lookup for cmov introduced in r349315 adds 7aae36e750b [X86] Add test case for PR39968. NFC adds 8178ac881e1 [llvm-mca] Move llvm-mca library to llvm/lib/MCA. adds c89c03b58be DebugInfo: Assume an absence of ranges or high_pc on a CU m [...] adds 6c9df68ed93 [AArch64] Re-run load/store optimizer after aggressive tail [...] adds 4c18d279009 [MIPS GlobalISel] Lower G_UADDE and narrowScalar G_ADD adds e52a0ade964 [AggressiveInstCombine] add test for rotate insertion point; NFC adds ef027ed59f3 Regenerate test in prep for SimplifyDemandedBits improvements. adds 4ed822d1608 [MCA] Don't assume that createMCInstrAnalysis() always retu [...] adds cc188a7f8bb Revert "DebugInfo: Assume an absence of ranges or high_pc o [...] adds 765a7627d9b [MCA] Add support for BeginGroup/EndGroup. adds e2e53c456d4 ARM: use acquire/release instruction variants when available. adds a7f5217bfb5 [MIPS GlobalISel] Remove switch statement (fix r349346 for MSVC) adds 18f6a2ac130 [MS Demangler] Add a helper function to print a Node as a string. adds a8e4afaa8d6 [PDB] Add some helper functions for working with scopes. adds 785589d4997 Add missing include file. adds 4a9ee89912a FastIsel: take care to update iterators when removing instr [...] adds 51120d77dfd [AMDGPU][MC][DOC] Updated AMD GPU assembler description adds e84034484b9 [InstSimplify] Simplify saturating add/sub + icmp adds 29dd0aa5bb9 [AMDGPU][MC][DOC] A fix for build failure in r349368 adds 1987714929e [TargetLowering] Add DemandedElts mask to SimplifyDemandedB [...] adds 23da1106786 [AMDGPU][MC][DOC] A fix for build failure in r349370 adds a54a3917dc9 AsmParser: test .double NaN and .double inf adds 1ea2e05be9e NFC: remove unused variable adds ffdc67646ac Convert (CMP (srl/shl X, C), 0) to (CMP (and X, C'), 0) whe [...] adds e23763e5beb [InstCombine] don't widen an arbitrary sequence of vector o [...] adds b7aabefcef8 [SelectionDAG] Fix noop detection for vectors in AssertZext [...] adds 2bf594e6caf [SDAG] Clarify the origin of chain in REG_SEQUENCE in comment, NFC adds 6789c7f5ced DebugInfo: Update gold plugin tests due to CU attribute reo [...] adds fae3cc44a92 [AggressiveInstCombine] convert rotate with guard branch in [...] adds f3b65bc4f2f [X86][SSE] Split SimplifyDemandedBitsForTargetNode X86ISD:: [...] adds 96b0873b25d [codeview] Flush labels before S_DEFRANGE* fragments adds c163300de59 [X86] Add T1MSKC and TZMSK to isDefConvertible used by opti [...] adds bcb7d765928 [WebAssembly] Fix assembler parsing of br_table. adds aa3674df5b5 [X86][SSE] Improve immediate vector shift known bits handling. adds 754733f9f9f [VFS] Add isLocal to ProxyFileSystem and add unit tests. adds 7c87d1aa46f hwasan: Move ctor into a comdat. adds 625d4a7a0d6 [X86] Add baseline tests for D55780 adds e1af89a06fd [FileCheck] Annotate input dump (1/7) adds 3fc136c9a9e [FileCheck] Annotate input dump (2/7) adds 7e86f826b9b [FileCheck] Annotate input dump (3/7) adds 8a1f7d65f79 [FileCheck] Annotate input dump (4/7) adds cf38e31d996 [FileCheck] Annotate input dump (5/7) adds 0b0cf2671a9 [FileCheck] Annotate input dump (6/7) adds c4c24a8093c [FileCheck] Annotate input dump (7/7) adds 302fa307d9f [FileCheck] Annotate input dump (final tweaks) adds 5ba1929dff5 Recommit r348806: DebugInfo: Use symbol difference for CU l [...] adds 80213579044 [codeview] Align symbol records to save 441MB during linkin [...] adds c0102bb7f8e [FileCheck] Try to fix test on windows due to r349418 adds 6022f00f350 [codeview] Update comment on aligning symbol records adds e0bb219a274 [Support] Fix GNU/kFreeBSD build adds 5ebd7af2ed1 [PowerPC] Improve vec_abs on P9 adds 234f7380ec8 [CaptureTracking] Pass MaxUsesToExplore from wrappers to th [...] adds 34ef4ce8299 [NFC] fix test case issue that with wrong label check. adds e33ed814287 [X86] Const correct some helper functions X86InstrInfo.cpp. NFC adds 7dc49173c67 [X86] Add test case for PR40060. NFC adds a2fa464a640 [NFC] Add new test to cover the lhs scheduling issue for P9. adds a032360a02d [PowerPC] Exploit power9 new instruction setb adds d662b752865 [PowerPC][NFC]Update vabsd cases with vselect test cases adds d67543f4164 [X86] Add test cases to show isel failing to match BMI blsm [...] adds 0b730b16a10 [AArch64] [MinGW] Allow enabling SEH exceptions adds 21db422faf6 Introduce control flow speculation tracking pass for AArch64 adds ce5a6119833 [X86][SSE] Replace (VSRLI (VSRAI X, Y), 31) -> (VSRLI X, 31) fold. adds 94f848082d6 [X86][SSE] Move VSRAI sign extend in reg fold into Simplify [...] adds d38a2490f32 AMDGPU/GlobalISel: Legalize/regbankselect fneg/fabs/fsub adds 563dd25b0e4 GlobalISel: Improve crash on invalid mapping adds 69008a07a6c SROA: preserve alignment tags on loads and stores. adds fe8acf3ad35 [TargetLowering] Fallback from SimplifyDemandedVectorElts t [...] adds 08319618c5c AMDGPU: Legalize/regbankselect fma adds 5af2f5e1047 AMDGPU: Legalize/regbankselect frame_index adds f14481850f5 [IPO][AVR] Create new Functions in the default address spac [...] adds 20b2043d8be [X86][SSE] Add 128-bit vector funnel shift tests adds 4acf41029c5 [X86][AVX] Add 256/512-bit vector funnel shift tests adds a0875a91cbb [AArch64] - Return address signing dwarf support adds 7fe679909d1 [MIPS GlobalISel] ClampScalar G_AND G_OR and G_XOR adds a002f3a8ef0 [llvm-dwarfdump] - Do not error out on R_X86_64_DTPOFF64/R_ [...] adds f6775ea3ff7 [docs] Improve HowToCrossCompilerBuiltinsOnArm adds 7c859dd19bc [SelectionDAG][X86] Fix [US](ADD|SUB)SAT vector legalizatio [...] adds 97b31b7b6f9 [X86] Use UADDSAT/USUBSAT instead of ADDUS/SUBUS adds 6b6826dc5bb [X86][SSE] Add shift combine 'out of range' tests with UNDEFs adds cbe186ea735 [gn build] Add build files for llvm-ar, llvm-nm, llvm-objdu [...] adds 907f5668d22 [gn build] Add build file for llvm-bcanalyzer adds 4770e3f8d89 [gn build] Add build file for llvm-pdbutil adds 046371adb09 [MIPS GlobalISel] Select G_SDIV, G_UDIV, G_SREM and G_UREM adds cfa2cf74cd9 [X86][SSE] Don't use 'sign bit select' vXi8 ROTL lowering f [...] adds 25333a14e77 [LoopUnroll] Honor '#pragma unroll' even with -fno-unroll-loops. adds 1b35b9e8551 [X86][SSE] Don't use 'sign bit select' vXi8 ROTL lowering f [...] adds 6b71eaac0a2 [LoopVectorize] Rename pass options. NFC. adds 2128fd1c561 Add FMF management to common fp intrinsics in GlobalIsel adds 1bc20f09859 [InstCombine] add tests for scalarization; NFC adds 93e27891ee4 [llvm-symbolizer] Omit stderr output when symbolizing a crash adds daedb463ee2 [CMake] Default options for faster executables on MSVC adds 6eed1f875bd Buildfix for r345516 (Clang compilation failing). adds 9c62d5728b3 [X86] Create PSUBUS from (add (umax X, C), -C) adds 6933dc723b2 [X86] Use SADDSAT/SSUBSAT instead of ADDS/SUBS adds a04db6078af [InstCombine] refactor isCheapToScalarize(); NFC adds 401feb8405f [X86] Don't use SplitOpsAndApply to create ISD::UADDSAT/ISD [...] adds 2d08f9b6516 [SCCP] Get rid of redundant call for getPredicateInfoFor (NFC). adds 6ea39d18c57 DebugInfo: Fix missing local imported entities after r349207 adds efd098d00b1 [AMDGPU] Removed the unnecessary operand size-check-assert [...] adds a0b99f282ac [InstCombine] Simplify cttz/ctlz + icmp eq/ne into mask check adds 1193c410de0 [X86] Add BSR to isUseDefConvertible. adds 7ad137666b7 Change the objc ARC optimizer to use the new objc.* intrinsics adds 9b284bbafd9 [llvm-mca] Dump mask in hex adds a9a68e43308 [llvm-mca] Update the Exynos test cases (NFC) adds 76d00595dda Fix MSVC dependency issue between Clang-tablegen and LLVM-tablegen adds e7e39420a0c [AARCH64] Added test case for PR40091 adds 974ebed4b6a [asan] In llvm.asan.globals, allow entries to be non-Global [...] adds 3a364fda921 Revert r349541 (Fix MSVC dependency issue between Clang-tab [...] adds faf7b5daf52 [InstCombine] auto-generate complete checks; NFC adds e15b0c691db [AArch64] Avoid crashing on .seh directives in assembly adds 7c9e35df238 Rewrite objc intrinsics to runtime methods in PreISelIntrin [...] adds 83544a50cc4 [LoopVectorize] auto-generate complete checks; NFC adds b9f7652283e [asan] Restore ODR-violation detection on vtables adds efdc43373b8 [LAA] Introduce enum for vectorization safety status (NFC). adds d2c49ab726c Add nonlazybind to objc_retain/objc_release when converting [...] adds 1a95f98a319 Preserve the linkage for objc* intrinsics as clang will set [...] adds 77376c854e2 [InstCombine] add tests for extract of vector load; NFC adds 6cd86b7cd2b [DebugInfo] Move several private headers to include directory adds ab30375a390 [llvm-mca] Improve test (NFC) adds a5a5e44a42e [AArch64] Fix instructions order (NFC) adds 174382c7045 [AArch64] Simplify the Exynos M3 pipeline model adds 3eabb09fb02 Add llvm-objdump man page adds afdba0b9d45 Re-land "Fix MSVC dependency issue between Clang-tablegen a [...] adds 4bc3cc6dbf2 [gn build] Add build file for llvm-objcopy adds 979b87d6b77 [PowerPC]Exploit P9 vabsdu for unsigned vselect patterns adds 11acfd478b7 Fix use-after-free with profile remapping. adds 79550f6c951 [bugpoint][PR29027] Reduce function attributes adds 35e719f872a [DebugInfo] Make AsmPrinter struct HandlerInfo and Handlers [...] adds e318fd6a26d [llvm-objcopy] Initial COFF support adds fcaab038f73 [llvm-objcopy] [COFF] Fix the Object forward declaration adds 028b8a60456 AMDGPU/GlobalISel: Regbankselect for fsub adds 331ffd31b3d [ARM GlobalISel] Support G_CONSTANT for Thumb2 adds 8cea59c941e AMDGPU/InsertWaitcnts: Update VGPR/SGPR bounds when bracket [...] adds 92b052b4844 [llvm-objdump] - Demangle the symbols when printing symbol [...] adds 927407d000e [llvm-objdump] - Fix BB. adds 8468ad25af6 [X86][SSE] Remove SSE ADDUS/SUBUS saturation intrinsics fro [...] adds de6808bcecb [SelectionDAG] Optional handling of UNDEF elements in match [...] adds 96c60eab748 [llvm-objdump] - Fix one more BB. adds f835629b79c AMDGPU: Use an ABS32_LO relocation for SCRATCH_RSRC_DWORD1 adds f8823459f33 [X86][SSE] Remove use of SSE ADDS/SUBS saturation intrinsic [...] adds a395f9853f0 Fix test MC/AMDGPU/reloc.s adds 0bc70d331a3 Let TableGen write output only if it changed, instead of do [...] adds cd3782549ec [TargetLowering] Fix propagation of undefs in zero extensio [...] adds e072f8b7259 [SelectionDAG] Optional handling of UNDEF elements in match [...] adds 0d195adc70c [SelectionDAG] Optional handling of UNDEF elements in match [...] adds ece16472bf8 [X86][SSE] Auto upgrade PADDUS/PSUBUS intrinsics to UADD_SA [...] adds 50ca11abbd0 Test commit adds 97de56dd446 [Object] Deduplicate long archive member names adds 725ddc363a1 [gn build] Merge r349605 adds 95dad60d32c [BPF] Generate BTF DebugInfo under BPF target adds 50eb45a1900 [ValueTracking] remove unused parameters from helper functi [...] adds 455880c4c1e [X86] Remove already upgraded llvm.x86.avx512.mask.padds/ps [...] adds 82da72ec40b Test commit adds 917e49e5a48 Regenerate test adds 27b9d229c3b [llvm-mca] Split test (NFC) adds 0a1392186ff [AArch64] Improve the Exynos M3 pipeline model adds 80ebdb91415 Revert r349517 "[CMake] Default options for faster executab [...] adds a7c670436df Revert r349517 "[CMake] Default options for faster executab [...] adds 6bad72cc707 [llvm-mca] Add an error handler for error from parseCodeRegions adds c3f9ab51440 [X86] Fix assert fails in pass X86AvoidSFBPass adds edc71ed5f57 [X86] Don't match TESTrr from (cmp (and X, Y), 0) during is [...] adds 4b7ed4f1030 [llvm-mca] Rename an error variable. adds 39d65885534 [GlobalISel][AArch64] Add support for @llvm.ceil adds dc8dd58c4c4 [ThinLTO] Remove dllimport attribute from locally defined symbols adds 838b95b50e9 llvm-dwarfdump: Improve/fix pretty printing of array dimensions adds 7bdfb496627 [X86] Remove a bunch of 'else' after returns in reduceVMULW [...] adds 97a44c83111 Re-land "Fix MSVC dependency issue between Clang-tablegen a [...] adds c93c3839e7f [BDCE][DemandedBits] Detect dead uses of undead instructions adds fc162457469 [gn build] Add build file for clang/lib/Basic and dependencies adds 576e6bc9fb2 Revert 349677, it contained a whole bunch of stuff I did no [...] adds f85aa0eda78 [gn build] Add build file for clang/lib/Basic and dependenc [...] adds 34890f3f7b7 [x86] add test to show ddup hole; NFC (PR37502) adds 8099039d57d [llvm-ar] Simplify string table get-or-insert pattern with [...] adds 992a545f9b6 Revert "[BDCE][DemandedBits] Detect dead uses of undead ins [...] adds f236e027c64 [AArch64] Use canonical copy idiom adds a403dca63b3 [AArch64] Improve Exynos predicates adds 289ef28882f [llvm-mca] Update Exynos test cases (NFC) adds d45f58d794c [llvm-mca] Rename directory for the Cortex tests (NFC) adds 1b084f058fb Test commit adds 2f8229eb68f Fix test commit adds ac0962643bb [CodeGenPrepare] Fix bad IR created by large offset GEP splitting. adds 934db57c7d6 AMDGPU: Add patterns for v4i16/v4f16 -> v4i16/v4f16 bitcasts adds 28950127b08 [X86] Remove TLI variable from ReplaceNodeResults. NFC adds d24b4c89122 [gn build] Add check-lld target and make it work adds 722838d767d [DwarfExpression] Fix a typo in a doxygen comment. NFC. adds 94edab2572a [gn build] Make `ninja check-lld` also run LLD's unit tests adds a94c9341011 [asan] Prevent folding of globals with redzones adds b7cd6fd37a7 [asan] Undo special treatment of linkonce_odr and weak_odr adds c6f008464fe AMDGPU/GlobalISel: Legality/regbankselect for atomicrmw/ato [...] adds e675164b4b1 AMDGPU/GlobalISel: RegBankSelect for fp conversions adds f6ea1298bb3 [binutils] NFC: fix clang-tidy warning: use empty() instead [...] adds 80fa53ba4eb [AArch64][GlobalISel] Implement selection og G_MERGE of two [...] adds 32e66b72648 [X86] Disable custom widening of signed/unsigned add/sub sa [...] adds 48efaa117f9 AMDGPU/GlobalISel: Fix ValueMapping tables for i1 adds 6493b367051 AMDGPU: Make i1/i64/v2i32 and/or/xor legal adds d0092eb5f9f [WebAssembly] Gate unimplemented SIMD ops on flag adds b15ca8072a1 Fix build errors introduced by r349712 on aarch64 bots. adds 347590f8fc8 [WebAssembly] Emit a splat for v128 IMPLICIT_DEF adds 42a382c2040 Introduce llvm.loop.parallel_accesses and llvm.access.group [...] adds f41808d09e5 [DAGCombiner] Fix a place that was creating a SIGN_EXTEND w [...] adds 26f63006cb9 [PowerPC] Implement the isSelectSupported() target hook adds 631b5bc6125 [HWASAN] Add support for memory intrinsics adds 768b489cfb9 [CodeGen][ExpandMemcmp] Add an option for allowing overlapp [...] adds 74d8f37a649 [NFC] Fix trailing comma after function. adds 0564fdd741d Revert r349731 "[CodeGen][ExpandMemcmp] Add an option for a [...] adds 8d01ccedc85 [MSan] Don't emit __msan_instrument_asm_load() calls adds 41901c01d44 [InstCombine][AMDGPU] Handle more buffer intrinsics adds 64002dd8fea [yaml2obj/obj2yaml] - Support dumping/parsing ABI version. adds 1224b482b42 [llvm-objcopy] - Do not drop the OS/ABI and ABIVersion fiel [...] adds 84d1605bd4a [X86] Change 'simple nonmem' intrinsic test to not use PADDSW adds 2033f0377d0 [llvm-objcopy] Use ELFOSABI_NONE instead of 0. NFC. adds 8581951a8a4 [X86] Update PADDSW/PSUBSW intrinsic usage with generic sat [...] adds 9fbd1c2311f [X86][SSE] Auto upgrade PADDS/PSUBS intrinsics to SADD_SAT/ [...] adds 6f90d45552d [SystemZ] Make better use of VLDEB adds d60a72a44b2 Re-land r349731 "[CodeGen][ExpandMemcmp] Add an option for [...] adds 182b5fec214 [SystemZ] Make better use of VGEF/VGEG adds 17177f1518b [SystemZ] Make better use of VLLEZ adds 12840a3e14d [gn build] Add build files for clang/lib/Lex and clang/lib/AST adds bc1c22befe4 [gn build] Add build files for clang/lib/{Analysis,Edit,Sema} adds dbbc3972320 [InstCombine] Make x86 PADDS/PSUBS constant folding tests generic adds 45e56bf0638 Fix gcc7 -Wdangling-else warning. NFCI. adds a564872860d [SystemZ] "Generic" vector assembler instructions shoud clobber CC adds 542c6ea9a58 [X86][AVX512] Don't custom lower v16i8 rotations. adds 55b9f76408b [RISCV] Properly evaluate fixup_riscv_pcrel_lo12 adds 0d758b2e709 [SelectionDAGBuilder] Enable funnel shift building to custo [...] new 865c650f23b Detect incorrect FileCheck variable CLI definition new b55d31dd34d FileCheck: Add support for numeric variables and expressions

This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this:

* -- * -- B -- O -- O -- O (5dc6d7ebade) \ N -- N -- N refs/heads/linaro-local/thomas.preudhomme/llvm-432-rebas [...]

You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B.

Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever.

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Summary of changes: CODE_OWNERS.TXT | 2 +- RELEASE_TESTERS.TXT | 4 +- cmake/modules/AddLLVM.cmake | 25 +- cmake/modules/TableGen.cmake | 26 +- docs/AMDGPU/AMDGPUAsmGFX7.rst | 1411 +++++++++++ docs/AMDGPU/AMDGPUAsmGFX8.rst | 1846 ++++++++++++++ docs/AMDGPU/AMDGPUAsmGFX9.rst | 2102 ++++++++++++++++ docs/AMDGPU/gfx7_addr_buf.rst | 24 + docs/AMDGPU/gfx7_addr_ds.rst | 17 + docs/AMDGPU/gfx7_addr_flat.rst | 17 + docs/AMDGPU/gfx7_addr_mimg.rst | 21 + docs/AMDGPU/gfx7_attr.rst | 30 + docs/AMDGPU/gfx7_base_smem_addr.rst | 17 + docs/AMDGPU/gfx7_base_smem_buf.rst | 17 + docs/AMDGPU/gfx7_bimm16.rst | 14 + docs/AMDGPU/gfx7_bimm32.rst | 14 + docs/AMDGPU/gfx7_data_buf_atomic128.rst | 21 + docs/AMDGPU/gfx7_data_buf_atomic32.rst | 21 + docs/AMDGPU/gfx7_data_buf_atomic64.rst | 21 + docs/AMDGPU/gfx7_data_mimg_atomic_cmp.rst | 27 + docs/AMDGPU/gfx7_data_mimg_atomic_reg.rst | 26 + docs/AMDGPU/gfx7_data_mimg_store.rst | 18 + docs/AMDGPU/gfx7_dst_buf_128.rst | 17 + docs/AMDGPU/gfx7_dst_buf_64.rst | 17 + docs/AMDGPU/gfx7_dst_buf_96.rst | 17 + docs/AMDGPU/gfx7_dst_buf_lds.rst | 21 + docs/AMDGPU/gfx7_dst_flat_atomic32.rst | 19 + docs/AMDGPU/gfx7_dst_flat_atomic64.rst | 19 + docs/AMDGPU/gfx7_dst_mimg_gather4.rst | 17 + docs/AMDGPU/gfx7_dst_mimg_regular.rst | 20 + docs/AMDGPU/gfx7_fimm32.rst | 14 + docs/AMDGPU/gfx7_hwreg.rst | 60 + docs/AMDGPU/gfx7_label.rst | 30 + docs/AMDGPU/gfx7_mod.rst | 14 + docs/AMDGPU/gfx7_msg.rst | 72 + docs/AMDGPU/gfx7_offset_buf.rst | 17 + docs/AMDGPU/gfx7_offset_smem.rst | 21 + docs/AMDGPU/gfx7_opt.rst | 14 + docs/AMDGPU/gfx7_param.rst | 22 + docs/AMDGPU/gfx7_ret.rst | 14 + docs/AMDGPU/gfx7_rsrc_buf.rst | 17 + docs/AMDGPU/gfx7_rsrc_mimg.rst | 17 + docs/AMDGPU/gfx7_samp_mimg.rst | 17 + docs/AMDGPU/gfx7_sdst128_0.rst | 17 + docs/AMDGPU/gfx7_sdst256_0.rst | 17 + docs/AMDGPU/gfx7_sdst32_0.rst | 17 + docs/AMDGPU/gfx7_sdst32_1.rst | 17 + docs/AMDGPU/gfx7_sdst32_2.rst | 17 + docs/AMDGPU/gfx7_sdst512_0.rst | 17 + docs/AMDGPU/gfx7_sdst64_0.rst | 17 + docs/AMDGPU/gfx7_sdst64_1.rst | 17 + docs/AMDGPU/gfx7_simm16.rst | 14 + docs/AMDGPU/gfx7_src32_0.rst | 17 + docs/AMDGPU/gfx7_src32_1.rst | 17 + docs/AMDGPU/gfx7_src32_2.rst | 17 + docs/AMDGPU/gfx7_src32_3.rst | 17 + docs/AMDGPU/gfx7_src64_0.rst | 17 + docs/AMDGPU/gfx7_src64_1.rst | 17 + docs/AMDGPU/gfx7_src64_2.rst | 17 + docs/AMDGPU/gfx7_src_exp.rst | 28 + docs/AMDGPU/gfx7_ssrc32_0.rst | 17 + docs/AMDGPU/gfx7_ssrc32_1.rst | 17 + docs/AMDGPU/gfx7_ssrc32_2.rst | 17 + docs/AMDGPU/gfx7_ssrc32_3.rst | 17 + docs/AMDGPU/gfx7_ssrc32_4.rst | 17 + docs/AMDGPU/gfx7_ssrc64_0.rst | 17 + docs/AMDGPU/gfx7_ssrc64_1.rst | 17 + docs/AMDGPU/gfx7_ssrc64_2.rst | 17 + docs/AMDGPU/gfx7_ssrc64_3.rst | 17 + docs/AMDGPU/gfx7_tgt.rst | 24 + docs/AMDGPU/gfx7_type_dev.rst | 14 + docs/AMDGPU/gfx7_uimm16.rst | 14 + docs/AMDGPU/gfx7_vcc_64.rst | 17 + docs/AMDGPU/gfx7_vdata128_0.rst | 17 + docs/AMDGPU/gfx7_vdata32_0.rst | 17 + docs/AMDGPU/gfx7_vdata64_0.rst | 17 + docs/AMDGPU/gfx7_vdata96_0.rst | 17 + docs/AMDGPU/gfx7_vdst128_0.rst | 17 + docs/AMDGPU/gfx7_vdst32_0.rst | 17 + docs/AMDGPU/gfx7_vdst64_0.rst | 17 + docs/AMDGPU/gfx7_vdst96_0.rst | 17 + docs/AMDGPU/gfx7_vsrc128_0.rst | 17 + docs/AMDGPU/gfx7_vsrc32_0.rst | 17 + docs/AMDGPU/gfx7_vsrc64_0.rst | 17 + docs/AMDGPU/gfx7_waitcnt.rst | 55 + docs/AMDGPU/gfx8_addr_buf.rst | 22 + docs/AMDGPU/gfx8_addr_ds.rst | 17 + docs/AMDGPU/gfx8_addr_flat.rst | 17 + docs/AMDGPU/gfx8_addr_mimg.rst | 21 + docs/AMDGPU/gfx8_attr.rst | 30 + docs/AMDGPU/gfx8_base_smem_addr.rst | 17 + docs/AMDGPU/gfx8_base_smem_buf.rst | 17 + docs/AMDGPU/gfx8_bimm16.rst | 14 + docs/AMDGPU/gfx8_bimm32.rst | 14 + docs/AMDGPU/gfx8_data_buf_atomic128.rst | 21 + docs/AMDGPU/gfx8_data_buf_atomic32.rst | 21 + docs/AMDGPU/gfx8_data_buf_atomic64.rst | 21 + docs/AMDGPU/gfx8_data_buf_d16_128.rst | 20 + docs/AMDGPU/gfx8_data_buf_d16_32.rst | 17 + docs/AMDGPU/gfx8_data_buf_d16_64.rst | 20 + docs/AMDGPU/gfx8_data_buf_d16_96.rst | 20 + docs/AMDGPU/gfx8_data_mimg_atomic_cmp.rst | 27 + docs/AMDGPU/gfx8_data_mimg_atomic_reg.rst | 26 + docs/AMDGPU/gfx8_data_mimg_store.rst | 18 + docs/AMDGPU/gfx8_data_mimg_store_d16.rst | 24 + docs/AMDGPU/gfx8_dst_buf_128.rst | 17 + docs/AMDGPU/gfx8_dst_buf_64.rst | 17 + docs/AMDGPU/gfx8_dst_buf_96.rst | 17 + docs/AMDGPU/gfx8_dst_buf_d16_128.rst | 21 + docs/AMDGPU/gfx8_dst_buf_d16_32.rst | 17 + docs/AMDGPU/gfx8_dst_buf_d16_64.rst | 21 + docs/AMDGPU/gfx8_dst_buf_d16_96.rst | 21 + docs/AMDGPU/gfx8_dst_buf_lds.rst | 21 + docs/AMDGPU/gfx8_dst_flat_atomic32.rst | 19 + docs/AMDGPU/gfx8_dst_flat_atomic64.rst | 19 + docs/AMDGPU/gfx8_dst_mimg_gather4.rst | 26 + docs/AMDGPU/gfx8_dst_mimg_regular.rst | 20 + docs/AMDGPU/gfx8_dst_mimg_regular_d16.rst | 26 + docs/AMDGPU/gfx8_fimm16.rst | 14 + docs/AMDGPU/gfx8_fimm32.rst | 14 + docs/AMDGPU/gfx8_hwreg.rst | 60 + docs/AMDGPU/gfx8_imm4.rst | 25 + docs/AMDGPU/gfx8_label.rst | 30 + docs/AMDGPU/gfx8_mod_dpp_sdwa_abs_neg.rst | 14 + docs/AMDGPU/gfx8_mod_sdwa_sext.rst | 14 + docs/AMDGPU/gfx8_mod_vop3_abs_neg.rst | 14 + docs/AMDGPU/gfx8_msg.rst | 72 + docs/AMDGPU/gfx8_offset_buf.rst | 17 + docs/AMDGPU/gfx8_offset_smem_load.rst | 17 + docs/AMDGPU/gfx8_offset_smem_store.rst | 17 + docs/AMDGPU/gfx8_opt.rst | 14 + docs/AMDGPU/gfx8_param.rst | 22 + docs/AMDGPU/gfx8_perm_smem.rst | 24 + docs/AMDGPU/gfx8_ret.rst | 14 + docs/AMDGPU/gfx8_rsrc_buf.rst | 17 + docs/AMDGPU/gfx8_rsrc_mimg.rst | 17 + docs/AMDGPU/gfx8_samp_mimg.rst | 17 + docs/AMDGPU/gfx8_sdata128_0.rst | 17 + docs/AMDGPU/gfx8_sdata32_0.rst | 17 + docs/AMDGPU/gfx8_sdata64_0.rst | 17 + docs/AMDGPU/gfx8_sdst128_0.rst | 17 + docs/AMDGPU/gfx8_sdst256_0.rst | 17 + docs/AMDGPU/gfx8_sdst32_0.rst | 17 + docs/AMDGPU/gfx8_sdst32_1.rst | 17 + docs/AMDGPU/gfx8_sdst32_2.rst | 17 + docs/AMDGPU/gfx8_sdst512_0.rst | 17 + docs/AMDGPU/gfx8_sdst64_0.rst | 17 + docs/AMDGPU/gfx8_sdst64_1.rst | 17 + docs/AMDGPU/gfx8_simm16.rst | 14 + docs/AMDGPU/gfx8_src32_0.rst | 17 + docs/AMDGPU/gfx8_src32_1.rst | 17 + docs/AMDGPU/gfx8_src64_0.rst | 17 + docs/AMDGPU/gfx8_src64_1.rst | 17 + docs/AMDGPU/gfx8_src_exp.rst | 28 + docs/AMDGPU/gfx8_ssrc32_0.rst | 17 + docs/AMDGPU/gfx8_ssrc32_1.rst | 17 + docs/AMDGPU/gfx8_ssrc32_2.rst | 17 + docs/AMDGPU/gfx8_ssrc32_3.rst | 17 + docs/AMDGPU/gfx8_ssrc32_4.rst | 17 + docs/AMDGPU/gfx8_ssrc64_0.rst | 17 + docs/AMDGPU/gfx8_ssrc64_1.rst | 17 + docs/AMDGPU/gfx8_ssrc64_2.rst | 17 + docs/AMDGPU/gfx8_ssrc64_3.rst | 17 + docs/AMDGPU/gfx8_tgt.rst | 24 + docs/AMDGPU/gfx8_type_dev.rst | 14 + docs/AMDGPU/gfx8_uimm16.rst | 14 + docs/AMDGPU/gfx8_vcc_64.rst | 17 + docs/AMDGPU/gfx8_vdata128_0.rst | 17 + docs/AMDGPU/gfx8_vdata32_0.rst | 17 + docs/AMDGPU/gfx8_vdata64_0.rst | 17 + docs/AMDGPU/gfx8_vdata96_0.rst | 17 + docs/AMDGPU/gfx8_vdst128_0.rst | 17 + docs/AMDGPU/gfx8_vdst32_0.rst | 17 + docs/AMDGPU/gfx8_vdst64_0.rst | 17 + docs/AMDGPU/gfx8_vdst96_0.rst | 17 + docs/AMDGPU/gfx8_vsrc128_0.rst | 17 + docs/AMDGPU/gfx8_vsrc32_0.rst | 17 + docs/AMDGPU/gfx8_vsrc64_0.rst | 17 + docs/AMDGPU/gfx8_waitcnt.rst | 55 + docs/AMDGPU/gfx9_addr_buf.rst | 22 + docs/AMDGPU/gfx9_addr_ds.rst | 17 + docs/AMDGPU/gfx9_addr_flat.rst | 17 + docs/AMDGPU/gfx9_addr_mimg.rst | 21 + docs/AMDGPU/gfx9_attr.rst | 30 + docs/AMDGPU/gfx9_base_smem_addr.rst | 17 + docs/AMDGPU/gfx9_base_smem_buf.rst | 17 + docs/AMDGPU/gfx9_base_smem_scratch.rst | 17 + docs/AMDGPU/gfx9_bimm16.rst | 14 + docs/AMDGPU/gfx9_bimm32.rst | 14 + docs/AMDGPU/gfx9_data_buf_atomic128.rst | 21 + docs/AMDGPU/gfx9_data_buf_atomic32.rst | 21 + docs/AMDGPU/gfx9_data_buf_atomic64.rst | 21 + docs/AMDGPU/gfx9_data_mimg_atomic_cmp.rst | 27 + docs/AMDGPU/gfx9_data_mimg_atomic_reg.rst | 26 + docs/AMDGPU/gfx9_data_mimg_store.rst | 18 + docs/AMDGPU/gfx9_data_mimg_store_d16.rst | 21 + docs/AMDGPU/gfx9_data_smem_atomic128.rst | 21 + docs/AMDGPU/gfx9_data_smem_atomic32.rst | 21 + docs/AMDGPU/gfx9_data_smem_atomic64.rst | 21 + docs/AMDGPU/gfx9_dst_buf_128.rst | 17 + docs/AMDGPU/gfx9_dst_buf_32.rst | 17 + docs/AMDGPU/gfx9_dst_buf_64.rst | 17 + docs/AMDGPU/gfx9_dst_buf_96.rst | 17 + docs/AMDGPU/gfx9_dst_buf_lds.rst | 21 + docs/AMDGPU/gfx9_dst_flat_atomic32.rst | 19 + docs/AMDGPU/gfx9_dst_flat_atomic64.rst | 19 + docs/AMDGPU/gfx9_dst_mimg_gather4.rst | 22 + docs/AMDGPU/gfx9_dst_mimg_regular.rst | 20 + docs/AMDGPU/gfx9_dst_mimg_regular_d16.rst | 22 + docs/AMDGPU/gfx9_fimm16.rst | 14 + docs/AMDGPU/gfx9_fimm32.rst | 14 + docs/AMDGPU/gfx9_hwreg.rst | 61 + docs/AMDGPU/gfx9_imm4.rst | 25 + docs/AMDGPU/gfx9_label.rst | 30 + docs/AMDGPU/gfx9_mad_type_dev.rst | 17 + docs/AMDGPU/gfx9_mod_dpp_sdwa_abs_neg.rst | 14 + docs/AMDGPU/gfx9_mod_sdwa_sext.rst | 14 + docs/AMDGPU/gfx9_mod_vop3_abs_neg.rst | 14 + docs/AMDGPU/gfx9_msg.rst | 72 + docs/AMDGPU/gfx9_offset_buf.rst | 17 + docs/AMDGPU/gfx9_offset_smem_buf.rst | 19 + docs/AMDGPU/gfx9_offset_smem_plain.rst | 22 + docs/AMDGPU/gfx9_opt.rst | 14 + docs/AMDGPU/gfx9_param.rst | 22 + docs/AMDGPU/gfx9_perm_smem.rst | 24 + docs/AMDGPU/gfx9_ret.rst | 14 + docs/AMDGPU/gfx9_rsrc_buf.rst | 17 + docs/AMDGPU/gfx9_rsrc_mimg.rst | 17 + docs/AMDGPU/gfx9_saddr_flat_global.rst | 19 + docs/AMDGPU/gfx9_saddr_flat_scratch.rst | 19 + docs/AMDGPU/gfx9_samp_mimg.rst | 17 + docs/AMDGPU/gfx9_sdata128_0.rst | 17 + docs/AMDGPU/gfx9_sdata32_0.rst | 17 + docs/AMDGPU/gfx9_sdata64_0.rst | 17 + docs/AMDGPU/gfx9_sdst128_0.rst | 17 + docs/AMDGPU/gfx9_sdst256_0.rst | 17 + docs/AMDGPU/gfx9_sdst32_0.rst | 17 + docs/AMDGPU/gfx9_sdst32_1.rst | 17 + docs/AMDGPU/gfx9_sdst32_2.rst | 17 + docs/AMDGPU/gfx9_sdst512_0.rst | 17 + docs/AMDGPU/gfx9_sdst64_0.rst | 17 + docs/AMDGPU/gfx9_sdst64_1.rst | 17 + docs/AMDGPU/gfx9_simm16.rst | 14 + docs/AMDGPU/gfx9_src32_0.rst | 17 + docs/AMDGPU/gfx9_src32_1.rst | 17 + docs/AMDGPU/gfx9_src64_0.rst | 17 + docs/AMDGPU/gfx9_src64_1.rst | 17 + docs/AMDGPU/gfx9_src_exp.rst | 28 + docs/AMDGPU/gfx9_ssrc32_0.rst | 17 + docs/AMDGPU/gfx9_ssrc32_1.rst | 17 + docs/AMDGPU/gfx9_ssrc32_2.rst | 17 + docs/AMDGPU/gfx9_ssrc32_3.rst | 17 + docs/AMDGPU/gfx9_ssrc32_4.rst | 17 + docs/AMDGPU/gfx9_ssrc64_0.rst | 17 + docs/AMDGPU/gfx9_ssrc64_1.rst | 17 + docs/AMDGPU/gfx9_ssrc64_2.rst | 17 + docs/AMDGPU/gfx9_ssrc64_3.rst | 17 + docs/AMDGPU/gfx9_tgt.rst | 24 + docs/AMDGPU/gfx9_type_dev.rst | 14 + docs/AMDGPU/gfx9_uimm16.rst | 14 + docs/AMDGPU/gfx9_vaddr_flat_global.rst | 22 + docs/AMDGPU/gfx9_vaddr_flat_scratch.rst | 19 + docs/AMDGPU/gfx9_vcc_64.rst | 17 + docs/AMDGPU/gfx9_vdata128_0.rst | 17 + docs/AMDGPU/gfx9_vdata32_0.rst | 17 + docs/AMDGPU/gfx9_vdata64_0.rst | 17 + docs/AMDGPU/gfx9_vdata96_0.rst | 17 + docs/AMDGPU/gfx9_vdst128_0.rst | 17 + docs/AMDGPU/gfx9_vdst32_0.rst | 17 + docs/AMDGPU/gfx9_vdst64_0.rst | 17 + docs/AMDGPU/gfx9_vdst96_0.rst | 17 + docs/AMDGPU/gfx9_vsrc128_0.rst | 17 + docs/AMDGPU/gfx9_vsrc32_0.rst | 17 + docs/AMDGPU/gfx9_vsrc64_0.rst | 17 + docs/AMDGPU/gfx9_waitcnt.rst | 56 + docs/AMDGPUAsmGFX7.rst | 1255 ---------- docs/AMDGPUAsmGFX8.rst | 1672 ------------- docs/AMDGPUAsmGFX9.rst | 1906 -------------- docs/AMDGPUInstructionNotation.rst | 110 + docs/AMDGPUInstructionSyntax.rst | 170 ++ docs/AMDGPUModifierSyntax.rst | 1248 ++++++++++ docs/AMDGPUOperandSyntax.rst | 1502 +++++------ docs/AMDGPUUsage.rst | 37 +- docs/AdvancedBuilds.rst | 9 + docs/CommandGuide/FileCheck.rst | 9 +- docs/HowToCrossCompileBuiltinsOnArm.rst | 191 +- docs/LangRef.rst | 132 +- docs/llvm-objdump.1 | 197 ++ include/llvm/ADT/SmallBitVector.h | 54 +- include/llvm/Analysis/LoopAccessAnalysis.h | 31 +- include/llvm/Analysis/LoopInfo.h | 26 + include/llvm/Analysis/LoopInfoImpl.h | 5 +- include/llvm/Analysis/ObjCARCAnalysisUtils.h | 38 +- include/llvm/Analysis/ObjCARCInstKind.h | 3 +- include/llvm/Analysis/TargetTransformInfo.h | 8 +- include/llvm/Analysis/VectorUtils.h | 20 +- include/llvm/BinaryFormat/Dwarf.def | 97 +- include/llvm/BinaryFormat/Dwarf.h | 9 +- include/llvm/BinaryFormat/Wasm.h | 27 +- include/llvm/CodeGen/AsmPrinter.h | 5 + include/llvm/CodeGen/AsmPrinterHandler.h | 74 + include/llvm/CodeGen/BasicTTIImpl.h | 28 +- include/llvm/CodeGen/DbgEntityHistoryCalculator.h | 87 + include/llvm/CodeGen/DebugHandlerBase.h | 138 ++ include/llvm/CodeGen/GlobalISel/CombinerHelper.h | 13 +- include/llvm/CodeGen/GlobalISel/CombinerInfo.h | 11 + .../llvm/CodeGen/GlobalISel/GISelChangeObserver.h | 29 +- include/llvm/CodeGen/GlobalISel/GISelWorkList.h | 58 +- include/llvm/CodeGen/Passes.h | 7 +- include/llvm/CodeGen/PreISelIntrinsicLowering.h | 3 +- include/llvm/CodeGen/SelectionDAGNodes.h | 9 +- include/llvm/CodeGen/TargetLowering.h | 21 +- .../llvm/CodeGen/TargetLoweringObjectFileImpl.h | 2 + .../llvm/DebugInfo/CodeView/SymbolRecordHelpers.h | 1 + include/llvm/DebugInfo/DWARF/DWARFContext.h | 4 + include/llvm/DebugInfo/DWARF/DWARFDebugFrame.h | 26 +- .../llvm/DebugInfo/PDB/Native/ModuleDebugStream.h | 2 + include/llvm/Demangle/MicrosoftDemangleNodes.h | 2 + include/llvm/IR/IntrinsicsX86.td | 24 +- include/llvm/IR/LLVMContext.h | 1 + include/llvm/IR/Module.h | 12 + include/llvm/IR/ModuleSummaryIndex.h | 50 +- include/llvm/IR/ModuleSummaryIndexYAML.h | 2 +- include/llvm/LTO/SummaryBasedOptimizations.h | 17 + include/llvm/MC/MCAssembler.h | 11 +- include/llvm/MC/MCCodeView.h | 2 +- include/llvm/MC/MCDwarf.h | 6 + include/llvm/MC/MCObjectFileInfo.h | 8 + include/llvm/MC/MCStreamer.h | 11 +- include/llvm/MCA/Context.h | 69 + include/llvm/MCA/HWEventListener.h | 156 ++ include/llvm/MCA/HardwareUnits/HardwareUnit.h | 33 + include/llvm/MCA/HardwareUnits/LSUnit.h | 207 ++ include/llvm/MCA/HardwareUnits/RegisterFile.h | 239 ++ include/llvm/MCA/HardwareUnits/ResourceManager.h | 360 +++ include/llvm/MCA/HardwareUnits/RetireControlUnit.h | 104 + include/llvm/MCA/HardwareUnits/Scheduler.h | 214 ++ include/llvm/MCA/InstrBuilder.h | 77 + include/llvm/MCA/Instruction.h | 544 ++++ include/llvm/MCA/Pipeline.h | 79 + include/llvm/MCA/SourceMgr.h | 57 + include/llvm/MCA/Stages/DispatchStage.h | 93 + include/llvm/MCA/Stages/EntryStage.h | 52 + include/llvm/MCA/Stages/ExecuteStage.h | 80 + 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lib/CodeGen/GlobalISel/GISelChangeObserver.cpp | 31 + lib/CodeGen/GlobalISel/IRTranslator.cpp | 77 +- lib/CodeGen/GlobalISel/Legalizer.cpp | 12 +- lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 89 +- lib/CodeGen/GlobalISel/LegalizerInfo.cpp | 2 +- lib/CodeGen/GlobalISel/RegBankSelect.cpp | 2 +- lib/CodeGen/MIRParser/MILexer.cpp | 2 + lib/CodeGen/MIRParser/MILexer.h | 2 + lib/CodeGen/MIRParser/MIParser.cpp | 123 +- lib/CodeGen/MachineOperand.cpp | 5 + lib/CodeGen/OptimizePHIs.cpp | 17 +- lib/CodeGen/PreISelIntrinsicLowering.cpp | 124 +- lib/CodeGen/RegAllocGreedy.cpp | 5 +- lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 341 +-- lib/CodeGen/SelectionDAG/FastISel.cpp | 9 + lib/CodeGen/SelectionDAG/InstrEmitter.cpp | 6 + lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp | 4 +- lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 4 + lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 73 +- lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 56 +- lib/CodeGen/SelectionDAG/TargetLowering.cpp | 188 +- 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| 14 +- lib/MC/MCWin64EH.cpp | 8 +- lib/MC/MachObjectWriter.cpp | 23 +- lib/MCA/CMakeLists.txt | 23 + lib/MCA/Context.cpp | 65 + lib/MCA/HWEventListener.cpp | 23 + lib/MCA/HardwareUnits/HardwareUnit.cpp | 25 + lib/MCA/HardwareUnits/LSUnit.cpp | 190 ++ lib/MCA/HardwareUnits/RegisterFile.cpp | 491 ++++ lib/MCA/HardwareUnits/ResourceManager.cpp | 328 +++ lib/MCA/HardwareUnits/RetireControlUnit.cpp | 88 + lib/MCA/HardwareUnits/Scheduler.cpp | 245 ++ lib/MCA/InstrBuilder.cpp | 682 +++++ lib/MCA/Instruction.cpp | 205 ++ {tools/llvm-mca/lib => lib/MCA}/LLVMBuild.txt | 0 lib/MCA/Pipeline.cpp | 97 + lib/MCA/Stages/DispatchStage.cpp | 193 ++ lib/MCA/Stages/EntryStage.cpp | 76 + lib/MCA/Stages/ExecuteStage.cpp | 219 ++ lib/MCA/Stages/InstructionTables.cpp | 69 + lib/MCA/Stages/RetireStage.cpp | 62 + lib/MCA/Stages/Stage.cpp | 29 + lib/MCA/Support.cpp | 79 + lib/Object/ArchiveWriter.cpp | 24 +- lib/Object/COFFObjectFile.cpp | 12 + lib/Object/ELF.cpp | 4 +- lib/Object/ModuleSymbolTable.cpp | 1 + lib/Object/ObjectFile.cpp | 8 + lib/Object/WasmObjectFile.cpp | 70 +- lib/ObjectYAML/ELFYAML.cpp | 1 + lib/Support/FileCheck.cpp | 483 ++-- lib/Support/Signals.cpp | 14 +- lib/Support/Unix/Path.inc | 2 +- lib/TableGen/Main.cpp | 32 +- lib/Target/AArch64/AArch64.h | 2 + lib/Target/AArch64/AArch64FastISel.cpp | 18 +- lib/Target/AArch64/AArch64FrameLowering.cpp | 6 + lib/Target/AArch64/AArch64ISelLowering.cpp | 18 +- lib/Target/AArch64/AArch64InstrInfo.cpp | 7 + lib/Target/AArch64/AArch64InstructionSelector.cpp | 83 +- lib/Target/AArch64/AArch64LegalizerInfo.cpp | 4 + lib/Target/AArch64/AArch64RegisterInfo.cpp | 4 + lib/Target/AArch64/AArch64SchedExynosM1.td | 8 +- lib/Target/AArch64/AArch64SchedExynosM3.td | 25 +- lib/Target/AArch64/AArch64SchedPredExynos.td | 80 +- lib/Target/AArch64/AArch64SchedPredicates.td | 12 +- lib/Target/AArch64/AArch64SpeculationHardening.cpp | 368 +++ lib/Target/AArch64/AArch64TargetMachine.cpp | 17 + lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp | 10 + lib/Target/AArch64/CMakeLists.txt | 1 + .../AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp | 3 + lib/Target/AMDGPU/AMDGPUAnnotateKernelFeatures.cpp | 68 +- lib/Target/AMDGPU/AMDGPUGenRegisterBankInfo.def | 63 +- lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 38 +- lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 63 +- lib/Target/AMDGPU/AMDGPURegisterBankInfo.h | 2 + lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 4 +- .../AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp | 6 +- lib/Target/AMDGPU/SIISelLowering.h | 2 +- lib/Target/AMDGPU/SIInsertWaitcnts.cpp | 3 + lib/Target/AMDGPU/SIInstructions.td | 2 + lib/Target/AMDGPU/SILoadStoreOptimizer.cpp | 363 +++ lib/Target/ARM/ARMFastISel.cpp | 3 +- lib/Target/ARM/ARMISelLowering.cpp | 3 +- lib/Target/ARM/ARMInstrThumb2.td | 14 +- lib/Target/ARM/ARMInstructionSelector.cpp | 127 +- lib/Target/ARM/ARMLegalizerInfo.cpp | 22 +- lib/Target/BPF/BPFAsmPrinter.cpp | 14 + lib/Target/BPF/BTF.def | 33 + lib/Target/BPF/BTF.h | 209 ++ lib/Target/BPF/BTFDebug.cpp | 759 ++++++ lib/Target/BPF/BTFDebug.h | 285 +++ lib/Target/BPF/CMakeLists.txt | 1 + lib/Target/Hexagon/HexagonPatterns.td | 60 +- lib/Target/Mips/MipsInstructionSelector.cpp | 27 + lib/Target/Mips/MipsLegalizerInfo.cpp | 52 +- lib/Target/Mips/MipsRegisterBankInfo.cpp | 4 + lib/Target/NVPTX/NVPTXISelLowering.cpp | 13 +- lib/Target/PowerPC/P9InstrResources.td | 2 +- lib/Target/PowerPC/PPCFastISel.cpp | 3 +- lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 256 +- lib/Target/PowerPC/PPCISelLowering.cpp | 229 +- lib/Target/PowerPC/PPCISelLowering.h | 23 + lib/Target/PowerPC/PPCInstr64Bit.td | 150 +- lib/Target/PowerPC/PPCInstrFormats.td | 21 +- lib/Target/PowerPC/PPCInstrHTM.td | 4 +- lib/Target/PowerPC/PPCInstrInfo.cpp | 1 + lib/Target/PowerPC/PPCInstrInfo.td | 341 ++- lib/Target/PowerPC/PPCInstrQPX.td | 50 +- lib/Target/PowerPC/PPCInstrSPE.td | 10 +- lib/Target/PowerPC/PPCInstrVSX.td | 151 +- lib/Target/PowerPC/README.txt | 1 + lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp | 39 + lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h | 7 +- lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp | 82 + lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.h | 10 + lib/Target/Sparc/AsmParser/SparcAsmParser.cpp | 55 + lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp | 23 + lib/Target/Sparc/InstPrinter/SparcInstPrinter.h | 2 + lib/Target/Sparc/SparcISelLowering.cpp | 16 +- lib/Target/Sparc/SparcInstrInfo.td | 12 +- lib/Target/SystemZ/SystemZISelDAGToDAG.cpp | 2 +- lib/Target/SystemZ/SystemZISelLowering.cpp | 51 +- lib/Target/SystemZ/SystemZISelLowering.h | 1 + lib/Target/SystemZ/SystemZInstrFormats.td | 23 +- lib/Target/SystemZ/SystemZInstrVector.td | 6 +- lib/Target/SystemZ/SystemZOperators.td | 42 +- lib/Target/SystemZ/SystemZRegisterInfo.cpp | 19 +- .../WebAssembly/AsmParser/WebAssemblyAsmParser.cpp | 39 +- .../InstPrinter/WebAssemblyInstPrinter.cpp | 51 +- .../InstPrinter/WebAssemblyInstPrinter.h | 1 + .../MCTargetDesc/WebAssemblyMCCodeEmitter.cpp | 8 - .../MCTargetDesc/WebAssemblyMCTargetDesc.h | 8 - lib/Target/WebAssembly/WebAssemblyFastISel.cpp | 2 + lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp | 2 + lib/Target/WebAssembly/WebAssemblyISelLowering.cpp | 6 + lib/Target/WebAssembly/WebAssemblyInstrControl.td | 28 +- lib/Target/WebAssembly/WebAssemblyInstrInfo.td | 1 + lib/Target/WebAssembly/WebAssemblyInstrSIMD.td | 13 +- lib/Target/WebAssembly/WebAssemblyRegStackify.cpp | 16 +- lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp | 27 +- lib/Target/X86/X86DiscriminateMemOps.cpp | 17 +- lib/Target/X86/X86FastISel.cpp | 3 +- lib/Target/X86/X86ISelDAGToDAG.cpp | 78 +- lib/Target/X86/X86ISelLowering.cpp | 815 +++--- lib/Target/X86/X86ISelLowering.h | 14 +- lib/Target/X86/X86InstrAVX512.td | 8 +- lib/Target/X86/X86InstrArithmetic.td | 11 +- lib/Target/X86/X86InstrFragmentsSIMD.td | 4 - lib/Target/X86/X86InstrInfo.cpp | 29 +- lib/Target/X86/X86InstrSSE.td | 16 +- lib/Target/X86/X86IntrinsicsInfo.h | 24 +- lib/Target/X86/X86TargetTransformInfo.cpp | 5 +- .../AggressiveInstCombine.cpp | 97 +- lib/Transforms/IPO/ArgumentPromotion.cpp | 3 +- lib/Transforms/IPO/DeadArgumentElimination.cpp | 4 +- lib/Transforms/IPO/ExtractGV.cpp | 1 + lib/Transforms/IPO/FunctionImport.cpp | 3 +- lib/Transforms/IPO/LowerTypeTests.cpp | 22 +- lib/Transforms/IPO/MergeFunctions.cpp | 8 +- lib/Transforms/IPO/PassManagerBuilder.cpp | 34 +- lib/Transforms/IPO/SampleProfile.cpp | 22 +- lib/Transforms/IPO/SyntheticCountsPropagation.cpp | 2 +- lib/Transforms/IPO/ThinLTOBitcodeWriter.cpp | 3 +- lib/Transforms/IPO/WholeProgramDevirt.cpp | 5 +- lib/Transforms/InstCombine/InstCombineCalls.cpp | 5 + lib/Transforms/InstCombine/InstCombineCasts.cpp | 15 +- lib/Transforms/InstCombine/InstCombineCompares.cpp | 25 +- .../InstCombine/InstCombineLoadStoreAlloca.cpp | 1 + lib/Transforms/InstCombine/InstCombinePHI.cpp | 1 + .../InstCombine/InstCombineSimplifyDemanded.cpp | 4 + .../InstCombine/InstCombineVectorOps.cpp | 58 +- .../InstCombine/InstructionCombining.cpp | 5 +- .../Instrumentation/AddressSanitizer.cpp | 25 +- .../Instrumentation/HWAddressSanitizer.cpp | 78 +- lib/Transforms/Instrumentation/InstrProfiling.cpp | 1 + lib/Transforms/Instrumentation/MemorySanitizer.cpp | 14 +- lib/Transforms/ObjCARC/ARCRuntimeEntryPoints.h | 74 +- lib/Transforms/ObjCARC/ObjCARCContract.cpp | 2 +- lib/Transforms/Scalar/EarlyCSE.cpp | 3 +- lib/Transforms/Scalar/GVNHoist.cpp | 2 +- lib/Transforms/Scalar/LoopUnrollPass.cpp | 54 +- lib/Transforms/Scalar/LoopVersioningLICM.cpp | 2 + lib/Transforms/Scalar/MemCpyOptimizer.cpp | 53 +- lib/Transforms/Scalar/NewGVN.cpp | 11 +- lib/Transforms/Scalar/SCCP.cpp | 2 +- lib/Transforms/Scalar/SROA.cpp | 71 +- lib/Transforms/Scalar/Scalarizer.cpp | 3 +- lib/Transforms/Scalar/WarnMissedTransforms.cpp | 5 + lib/Transforms/Utils/FunctionImportUtils.cpp | 19 +- lib/Transforms/Utils/InlineFunction.cpp | 26 +- lib/Transforms/Utils/Local.cpp | 39 +- lib/Transforms/Utils/LoopUtils.cpp | 51 +- lib/Transforms/Utils/SimplifyCFG.cpp | 3 +- .../Vectorize/LoopVectorizationLegality.cpp | 13 +- lib/Transforms/Vectorize/LoopVectorize.cpp | 19 +- lib/Transforms/Vectorize/SLPVectorizer.cpp | 8 +- lib/XRay/InstrumentationMap.cpp | 45 +- test/Analysis/CostModel/X86/reduction.ll | 82 +- .../LoopInfo/annotated-parallel-complex.ll | 91 + .../Analysis/LoopInfo/annotated-parallel-simple.ll | 37 + test/Bitcode/summary_version.ll | 2 +- test/Bitcode/thinlto-alias.ll | 2 +- .../thinlto-function-summary-callgraph-pgo.ll | 2 +- ...o-function-summary-callgraph-profile-summary.ll | 2 +- ...ion-summary-callgraph-sample-profile-summary.ll | 2 +- test/Bitcode/thinlto-function-summary-callgraph.ll | 2 +- test/Bitcode/thinlto-synthetic-count-flag.ll | 21 + test/BugPoint/func-attrs-keyval.ll | 11 + test/BugPoint/func-attrs.ll | 11 + .../AArch64/GlobalISel/arm64-irtranslator.ll | 73 +- .../AArch64/GlobalISel/legalize-load-fewerElts.mir | 39 - .../GlobalISel/legalize-load-store-fewerElts.mir | 54 + .../GlobalISel/legalizer-info-validation.mir | 3 + ...galizercombiner-extending-loads-cornercases.mir | 61 +- test/CodeGen/AArch64/GlobalISel/select-ceil.mir | 93 + .../AArch64/GlobalISel/select-scalar-merge.mir | 34 + test/CodeGen/AArch64/O0-pipeline.ll | 1 + test/CodeGen/AArch64/O3-pipeline.ll | 2 + test/CodeGen/AArch64/aarch64-smull.ll | 11 +- test/CodeGen/AArch64/arm64-neon-copy.ll | 763 ++++-- test/CodeGen/AArch64/arm64-vcvt.ll | 6 + test/CodeGen/AArch64/fast-isel-erase.ll | 25 + .../AArch64/ldst-opt-after-block-placement.ll | 51 + test/CodeGen/AArch64/pr40091.ll | 22 + test/CodeGen/AArch64/sign-return-address.ll | 22 +- .../AArch64/speculation-hardening-dagisel.ll | 71 + test/CodeGen/AArch64/speculation-hardening.ll | 156 ++ test/CodeGen/AArch64/speculation-hardening.mir | 117 + test/CodeGen/AArch64/wineh-mingw.ll | 48 + test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir | 59 +- .../AMDGPU/GlobalISel/legalize-atomic-cmpxchg.mir | 71 + .../AMDGPU/GlobalISel/legalize-atomicrmw-add.mir | 63 + .../AMDGPU/GlobalISel/legalize-atomicrmw-and.mir | 63 + .../AMDGPU/GlobalISel/legalize-atomicrmw-max.mir | 63 + .../AMDGPU/GlobalISel/legalize-atomicrmw-min.mir | 63 + .../AMDGPU/GlobalISel/legalize-atomicrmw-nand.mir | 22 + .../AMDGPU/GlobalISel/legalize-atomicrmw-or.mir | 63 + .../AMDGPU/GlobalISel/legalize-atomicrmw-sub.mir | 63 + .../AMDGPU/GlobalISel/legalize-atomicrmw-umax.mir | 63 + .../AMDGPU/GlobalISel/legalize-atomicrmw-umin.mir | 63 + .../GlobalISel/legalize-atomicrmw-xchg-flat.mir | 36 + .../AMDGPU/GlobalISel/legalize-atomicrmw-xchg.mir | 63 + .../AMDGPU/GlobalISel/legalize-atomicrmw-xor.mir | 63 + .../AMDGPU/GlobalISel/legalize-block-addr.mir | 28 + test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir | 25 + test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir | 35 + test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir | 25 + .../CodeGen/AMDGPU/GlobalISel/legalize-fptrunc.mir | 17 + test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir | 36 + test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir | 59 +- test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir | 59 +- .../AMDGPU/GlobalISel/regbankselect-and.mir | 156 +- .../GlobalISel/regbankselect-atomic-cmpxchg.mir | 66 + .../GlobalISel/regbankselect-atomicrmw-add.mir | 57 + .../GlobalISel/regbankselect-atomicrmw-and.mir | 57 + .../GlobalISel/regbankselect-atomicrmw-max.mir | 57 + .../GlobalISel/regbankselect-atomicrmw-min.mir | 57 + .../GlobalISel/regbankselect-atomicrmw-or.mir | 57 + .../GlobalISel/regbankselect-atomicrmw-sub.mir | 57 + .../GlobalISel/regbankselect-atomicrmw-umax.mir | 57 + .../GlobalISel/regbankselect-atomicrmw-umin.mir | 57 + .../GlobalISel/regbankselect-atomicrmw-xchg.mir | 57 + .../GlobalISel/regbankselect-atomicrmw-xor.mir | 57 + .../AMDGPU/GlobalISel/regbankselect-block-addr.mir | 29 + .../AMDGPU/GlobalISel/regbankselect-fabs.mir | 35 + .../AMDGPU/GlobalISel/regbankselect-fma.mir | 148 ++ .../AMDGPU/GlobalISel/regbankselect-fneg.mir | 35 + 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