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from 0efe904de8c RISC-V: Always register vector built-in functions during LT [...] new 05e7d542bcd RISC-V: Handle overlap in expand_vec_perm PR121742. new 7ec702536bb RISC-V: Use correct target in expand_vec_perm [PR121780].
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Summary of changes: gcc/config/riscv/riscv-v.cc | 11 +++-- .../gcc.target/riscv/rvv/autovec/pr121742.c | 30 ++++++++++++ .../gcc.target/riscv/rvv/autovec/pr121780.c | 47 +++++++++++++++++++ .../gcc.target/riscv/rvv/autovec/pr121781.c | 53 ++++++++++++++++++++++ 4 files changed, 138 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr121742.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr121780.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr121781.c