[Tcwg-commits] [gcc] branch master updated (b7e4f61c3e7 -> 79ef372fa41)

This is an automated email from the git hooks/post-receive script.

unknown user pushed a change to branch master in repository gcc.

from b7e4f61c3e7 RISC-V: Add vadc C++ API tests new dca23bf0bbe RISC-V: Add vmadc/vmsbc C/C++ API support new c8c7b4b32d8 RISC-V: Add vmadc C API tests new bd5c5d2eaf1 RISC-V: Add vmsbc C API tests new 485c710b4e6 RISC-V: Add vmadc C++ API tests new 30eedd6a4fc RISC-V: Add vmsbc C++ API tests new 6271a07219a RISC-V: Add vnsrl/vnsra/vncvt/vmerge/vmv C/C++ support new 10e999a3abd RISC-V: Add vnsrl C API tests new eeec45d2923 RISC-V: Add vnsra C API tests new fb03f2acfb7 RISC-V: Add vncvt C API tests new c1294253310 RISC-V: Add vmv C API tests new 4852c719a1a RISC-V: Add vmv.v.x C API tests new c0ea34be11c RISC-V: Add vmerge C API tests new 0b7dd2f4799 RISC-V: Add vnsrl C++ API tests new 484ea18ffae RISC-V: Add vnsra C++ API tests new 9a1c81afd55 RISC-V: Add vncvt/vmv C++ API tests new 79ef372fa41 RISC-V: Add vmerge C++ API test

The 16 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.

Summary of changes: gcc/config/riscv/constraints.md | 13 - gcc/config/riscv/predicates.md | 7 +- gcc/config/riscv/riscv-vector-builtins-bases.cc | 140 ++++ gcc/config/riscv/riscv-vector-builtins-bases.h | 7 + .../riscv/riscv-vector-builtins-functions.def | 25 +- gcc/config/riscv/riscv-vector-builtins-shapes.cc | 82 +++ gcc/config/riscv/riscv-vector-builtins-shapes.h | 3 + gcc/config/riscv/riscv-vector-builtins.cc | 149 ++++- gcc/config/riscv/riscv-vector-builtins.def | 5 +- gcc/config/riscv/riscv-vector-builtins.h | 11 + gcc/config/riscv/riscv.cc | 42 +- gcc/config/riscv/vector-iterators.md | 6 + gcc/config/riscv/vector.md | 733 ++++++++++++++++++++- .../g++.target/riscv/rvv/base/vmadc_vv-1.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmadc_vv-2.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmadc_vv-3.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmadc_vvm-1.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmadc_vvm-2.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmadc_vvm-3.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmadc_vx_rv32-1.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmadc_vx_rv32-2.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmadc_vx_rv32-3.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmadc_vx_rv64-1.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmadc_vx_rv64-2.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmadc_vx_rv64-3.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmadc_vxm_rv32-1.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmadc_vxm_rv32-2.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmadc_vxm_rv32-3.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmadc_vxm_rv64-1.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmadc_vxm_rv64-2.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmadc_vxm_rv64-3.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmerge_vvm-1.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmerge_vvm-2.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmerge_vvm-3.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmerge_vvm-4.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmerge_vvm-5.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmerge_vvm-6.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmerge_vvm_tu-1.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmerge_vvm_tu-2.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmerge_vvm_tu-3.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmerge_vvm_tu-4.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmerge_vvm_tu-5.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmerge_vvm_tu-6.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmerge_vxm_rv32-1.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmerge_vxm_rv32-2.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmerge_vxm_rv32-3.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmerge_vxm_rv64-1.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmerge_vxm_rv64-2.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmerge_vxm_rv64-3.C | 292 ++++++++ .../riscv/rvv/base/vmerge_vxm_tu_rv32-1.C | 289 ++++++++ .../riscv/rvv/base/vmerge_vxm_tu_rv32-2.C | 289 ++++++++ .../riscv/rvv/base/vmerge_vxm_tu_rv32-3.C | 289 ++++++++ .../riscv/rvv/base/vmerge_vxm_tu_rv64-1.C | 292 ++++++++ .../riscv/rvv/base/vmerge_vxm_tu_rv64-2.C | 292 ++++++++ .../riscv/rvv/base/vmerge_vxm_tu_rv64-3.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsbc_vv-1.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsbc_vv-2.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsbc_vv-3.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsbc_vvm-1.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsbc_vvm-2.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsbc_vvm-3.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsbc_vx_rv32-1.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmsbc_vx_rv32-2.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmsbc_vx_rv32-3.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmsbc_vx_rv64-1.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsbc_vx_rv64-2.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsbc_vx_rv64-3.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsbc_vxm_rv32-1.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmsbc_vxm_rv32-2.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmsbc_vxm_rv32-3.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmsbc_vxm_rv64-1.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsbc_vxm_rv64-2.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsbc_vxm_rv64-3.C | 292 ++++++++ gcc/testsuite/g++.target/riscv/rvv/base/vmv_v-1.C | 392 +++++++++++ .../g++.target/riscv/rvv/base/vmv_v_tu-1.C | 392 +++++++++++ .../g++.target/riscv/rvv/base/vmv_v_x_rv32-1.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmv_v_x_rv32-2.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmv_v_x_rv32-3.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmv_v_x_rv64-1.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmv_v_x_rv64-2.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmv_v_x_rv64-3.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vncvt_x-1.C | 396 +++++++++++ .../g++.target/riscv/rvv/base/vncvt_x-2.C | 396 +++++++++++ .../g++.target/riscv/rvv/base/vncvt_x-3.C | 396 +++++++++++ .../g++.target/riscv/rvv/base/vncvt_x_mu-1.C | 201 ++++++ .../g++.target/riscv/rvv/base/vncvt_x_mu-2.C | 201 ++++++ .../g++.target/riscv/rvv/base/vncvt_x_mu-3.C | 201 ++++++ .../g++.target/riscv/rvv/base/vncvt_x_tu-1.C | 201 ++++++ .../g++.target/riscv/rvv/base/vncvt_x_tu-2.C | 201 ++++++ .../g++.target/riscv/rvv/base/vncvt_x_tu-3.C | 201 ++++++ .../g++.target/riscv/rvv/base/vncvt_x_tum-1.C | 201 ++++++ .../g++.target/riscv/rvv/base/vncvt_x_tum-2.C | 201 ++++++ .../g++.target/riscv/rvv/base/vncvt_x_tum-3.C | 201 ++++++ .../g++.target/riscv/rvv/base/vncvt_x_tumu-1.C | 201 ++++++ .../g++.target/riscv/rvv/base/vncvt_x_tumu-2.C | 201 ++++++ .../g++.target/riscv/rvv/base/vncvt_x_tumu-3.C | 201 ++++++ .../g++.target/riscv/rvv/base/vnsra_vv-1.C | 216 ++++++ .../g++.target/riscv/rvv/base/vnsra_vv-2.C | 216 ++++++ .../g++.target/riscv/rvv/base/vnsra_vv-3.C | 216 ++++++ .../g++.target/riscv/rvv/base/vnsra_vv_mu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsra_vv_mu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsra_vv_mu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsra_vv_tu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsra_vv_tu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsra_vv_tu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsra_vv_tum-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsra_vv_tum-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsra_vv_tum-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsra_vv_tumu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsra_vv_tumu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsra_vv_tumu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsra_vx-1.C | 216 ++++++ .../g++.target/riscv/rvv/base/vnsra_vx-2.C | 216 ++++++ .../g++.target/riscv/rvv/base/vnsra_vx-3.C | 216 ++++++ .../g++.target/riscv/rvv/base/vnsra_vx_mu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsra_vx_mu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsra_vx_mu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsra_vx_tu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsra_vx_tu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsra_vx_tu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsra_vx_tum-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsra_vx_tum-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsra_vx_tum-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsra_vx_tumu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsra_vx_tumu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsra_vx_tumu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsrl_vv-1.C | 216 ++++++ .../g++.target/riscv/rvv/base/vnsrl_vv-2.C | 216 ++++++ .../g++.target/riscv/rvv/base/vnsrl_vv-3.C | 216 ++++++ .../g++.target/riscv/rvv/base/vnsrl_vv_mu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsrl_vv_mu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsrl_vv_mu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsrl_vv_tu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsrl_vv_tu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsrl_vv_tu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsrl_vv_tum-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsrl_vv_tum-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsrl_vv_tum-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsrl_vv_tumu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsrl_vv_tumu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsrl_vv_tumu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsrl_vx-1.C | 216 ++++++ .../g++.target/riscv/rvv/base/vnsrl_vx-2.C | 216 ++++++ .../g++.target/riscv/rvv/base/vnsrl_vx-3.C | 216 ++++++ .../g++.target/riscv/rvv/base/vnsrl_vx_mu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsrl_vx_mu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsrl_vx_mu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsrl_vx_tu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsrl_vx_tu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsrl_vx_tu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsrl_vx_tum-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsrl_vx_tum-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsrl_vx_tum-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsrl_vx_tumu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsrl_vx_tumu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vnsrl_vx_tumu-3.C | 111 ++++ .../riscv/rvv/base/{vadc-1.c => vmadc-1.c} | 12 +- gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-2.c | 43 ++ .../riscv/rvv/base/{vadc-3.c => vmadc-3.c} | 48 +- .../riscv/rvv/base/{vadc-4.c => vmadc-4.c} | 50 +- .../riscv/rvv/base/{vadc-1.c => vmadc-5.c} | 13 +- gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-6.c | 43 ++ gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-7.c | 85 +++ gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-8.c | 86 +++ .../gcc.target/riscv/rvv/base/vmadc_vv-1.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmadc_vv-2.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmadc_vv-3.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmadc_vvm-1.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmadc_vvm-2.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmadc_vvm-3.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmadc_vx_rv32-1.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmadc_vx_rv32-2.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmadc_vx_rv32-3.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmadc_vx_rv64-1.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmadc_vx_rv64-2.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmadc_vx_rv64-3.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmadc_vxm_rv32-1.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmadc_vxm_rv32-2.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmadc_vxm_rv32-3.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmadc_vxm_rv64-1.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmadc_vxm_rv64-2.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmadc_vxm_rv64-3.c | 292 ++++++++ .../riscv/rvv/base/{vadc-1.c => vmerge-1.c} | 10 +- .../riscv/rvv/base/{vadc-2.c => vmerge-2.c} | 23 +- .../riscv/rvv/base/{vadc-3.c => vmerge-3.c} | 34 +- .../riscv/rvv/base/{vadc-4.c => vmerge-4.c} | 36 +- .../gcc.target/riscv/rvv/base/vmerge_vvm-1.c | 69 ++ .../gcc.target/riscv/rvv/base/vmerge_vvm-2.c | 69 ++ .../gcc.target/riscv/rvv/base/vmerge_vvm-3.c | 69 ++ .../gcc.target/riscv/rvv/base/vmerge_vvm-4.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmerge_vvm-5.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmerge_vvm-6.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmerge_vvm_tu-1.c | 69 ++ .../gcc.target/riscv/rvv/base/vmerge_vvm_tu-2.c | 69 ++ .../gcc.target/riscv/rvv/base/vmerge_vvm_tu-3.c | 69 ++ .../gcc.target/riscv/rvv/base/vmerge_vvm_tu-4.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmerge_vvm_tu-5.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmerge_vvm_tu-6.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmerge_vxm_rv32-1.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmerge_vxm_rv32-2.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmerge_vxm_rv32-3.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmerge_vxm_rv64-1.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmerge_vxm_rv64-2.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmerge_vxm_rv64-3.c | 292 ++++++++ .../riscv/rvv/base/vmerge_vxm_tu_rv32-1.c | 289 ++++++++ .../riscv/rvv/base/vmerge_vxm_tu_rv32-2.c | 289 ++++++++ .../riscv/rvv/base/vmerge_vxm_tu_rv32-3.c | 289 ++++++++ .../riscv/rvv/base/vmerge_vxm_tu_rv64-1.c | 292 ++++++++ .../riscv/rvv/base/vmerge_vxm_tu_rv64-2.c | 292 ++++++++ .../riscv/rvv/base/vmerge_vxm_tu_rv64-3.c | 292 ++++++++ .../riscv/rvv/base/{vadc-1.c => vmsbc-1.c} | 12 +- gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc-2.c | 42 ++ .../riscv/rvv/base/{vsbc-3.c => vmsbc-3.c} | 46 +- .../riscv/rvv/base/{vsbc-4.c => vmsbc-4.c} | 48 +- .../riscv/rvv/base/{vadc-1.c => vmsbc-5.c} | 13 +- gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc-6.c | 42 ++ gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc-7.c | 84 +++ gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc-8.c | 84 +++ .../gcc.target/riscv/rvv/base/vmsbc_vv-1.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsbc_vv-2.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsbc_vv-3.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsbc_vvm-1.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsbc_vvm-2.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsbc_vvm-3.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsbc_vx_rv32-1.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmsbc_vx_rv32-2.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmsbc_vx_rv32-3.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmsbc_vx_rv64-1.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsbc_vx_rv64-2.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsbc_vx_rv64-3.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsbc_vxm_rv32-1.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmsbc_vxm_rv32-2.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmsbc_vxm_rv32-3.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmsbc_vxm_rv64-1.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsbc_vxm_rv64-2.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsbc_vxm_rv64-3.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmv_v_v-1.c | 276 ++++++++ .../gcc.target/riscv/rvv/base/vmv_v_v-2.c | 276 ++++++++ .../gcc.target/riscv/rvv/base/vmv_v_v-3.c | 276 ++++++++ .../gcc.target/riscv/rvv/base/vmv_v_v_tu-1.c | 276 ++++++++ .../gcc.target/riscv/rvv/base/vmv_v_v_tu-2.c | 276 ++++++++ .../gcc.target/riscv/rvv/base/vmv_v_v_tu-3.c | 276 ++++++++ .../gcc.target/riscv/rvv/base/vmv_v_x_rv32-1.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmv_v_x_rv32-2.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmv_v_x_rv32-3.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmv_v_x_rv64-1.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmv_v_x_rv64-2.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmv_v_x_rv64-3.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmv_v_x_tu_rv32-1.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmv_v_x_tu_rv32-2.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmv_v_x_tu_rv32-3.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmv_v_x_tu_rv64-1.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmv_v_x_tu_rv64-2.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmv_v_x_tu_rv64-3.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vncvt_x-1.c | 201 ++++++ .../gcc.target/riscv/rvv/base/vncvt_x-2.c | 201 ++++++ .../gcc.target/riscv/rvv/base/vncvt_x-3.c | 201 ++++++ .../gcc.target/riscv/rvv/base/vncvt_x_m-1.c | 201 ++++++ .../gcc.target/riscv/rvv/base/vncvt_x_m-2.c | 201 ++++++ .../gcc.target/riscv/rvv/base/vncvt_x_m-3.c | 201 ++++++ .../gcc.target/riscv/rvv/base/vncvt_x_mu-1.c | 201 ++++++ .../gcc.target/riscv/rvv/base/vncvt_x_mu-2.c | 201 ++++++ .../gcc.target/riscv/rvv/base/vncvt_x_mu-3.c | 201 ++++++ .../gcc.target/riscv/rvv/base/vncvt_x_tu-1.c | 201 ++++++ .../gcc.target/riscv/rvv/base/vncvt_x_tu-2.c | 201 ++++++ .../gcc.target/riscv/rvv/base/vncvt_x_tu-3.c | 201 ++++++ .../gcc.target/riscv/rvv/base/vncvt_x_tum-1.c | 201 ++++++ .../gcc.target/riscv/rvv/base/vncvt_x_tum-2.c | 201 ++++++ .../gcc.target/riscv/rvv/base/vncvt_x_tum-3.c | 201 ++++++ .../gcc.target/riscv/rvv/base/vncvt_x_tumu-1.c | 201 ++++++ .../gcc.target/riscv/rvv/base/vncvt_x_tumu-2.c | 201 ++++++ .../gcc.target/riscv/rvv/base/vncvt_x_tumu-3.c | 201 ++++++ .../gcc.target/riscv/rvv/base/vnsra_wv-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wv-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wv-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wv_m-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wv_m-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wv_m-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wv_mu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wv_mu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wv_mu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wv_tu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wv_tu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wv_tu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wv_tum-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wv_tum-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wv_tum-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wv_tumu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wv_tumu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wv_tumu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wx-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wx-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wx-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wx_m-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wx_m-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wx_m-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wx_mu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wx_mu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wx_mu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wx_tu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wx_tu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wx_tu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wx_tum-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wx_tum-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wx_tum-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wx_tumu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wx_tumu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsra_wx_tumu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wv-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wv-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wv-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wv_m-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wv_m-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wv_m-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wv_mu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wv_mu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wv_mu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wv_tu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wv_tu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wv_tu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wv_tum-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wv_tum-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wv_tum-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wv_tumu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wv_tumu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wv_tumu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wx-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wx-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wx-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wx_m-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wx_m-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wx_m-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wx_mu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wx_mu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wx_mu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wx_tu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wx_tu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wx_tu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wx_tum-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wx_tum-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wx_tum-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wx_tumu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wx_tumu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vnsrl_wx_tumu-3.c | 111 ++++ 344 files changed, 66241 insertions(+), 229 deletions(-) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vvm-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vvm-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vvm-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vxm_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vxm_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vxm_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vxm_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vxm_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vxm_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vvm-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vvm-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vvm-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vvm-4.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vvm-5.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vvm-6.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vvm_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vvm_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vvm_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vvm_tu-4.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vvm_tu-5.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vvm_tu-6.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vxm_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vxm_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vxm_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vxm_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vxm_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vxm_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vxm_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vxm_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vxm_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vxm_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vxm_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vxm_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vvm-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vvm-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vvm-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vxm_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vxm_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vxm_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vxm_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vxm_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vxm_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmv_v-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmv_v_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmv_v_x_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmv_v_x_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmv_v_x_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmv_v_x_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmv_v_x_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmv_v_x_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tumu-3.C copy gcc/testsuite/gcc.target/riscv/rvv/base/{vadc-1.c => vmadc-1.c} (56%) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-2.c copy gcc/testsuite/gcc.target/riscv/rvv/base/{vadc-3.c => vmadc-3.c} (52%) copy gcc/testsuite/gcc.target/riscv/rvv/base/{vadc-4.c => vmadc-4.c} (50%) copy gcc/testsuite/gcc.target/riscv/rvv/base/{vadc-1.c => vmadc-5.c} (51%) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vvm-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vvm-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vvm-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vxm_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vxm_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vxm_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vxm_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vxm_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vxm_rv64-3.c copy gcc/testsuite/gcc.target/riscv/rvv/base/{vadc-1.c => vmerge-1.c} (63%) copy gcc/testsuite/gcc.target/riscv/rvv/base/{vadc-2.c => vmerge-2.c} (56%) copy gcc/testsuite/gcc.target/riscv/rvv/base/{vadc-3.c => vmerge-3.c} (61%) copy gcc/testsuite/gcc.target/riscv/rvv/base/{vadc-4.c => vmerge-4.c} (59%) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm_tu-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm_tu-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm_tu-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_tu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_tu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_tu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_tu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_tu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_tu_rv64-3.c copy gcc/testsuite/gcc.target/riscv/rvv/base/{vadc-1.c => vmsbc-1.c} (56%) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc-2.c copy gcc/testsuite/gcc.target/riscv/rvv/base/{vsbc-3.c => vmsbc-3.c} (53%) copy gcc/testsuite/gcc.target/riscv/rvv/base/{vsbc-4.c => vmsbc-4.c} (52%) copy gcc/testsuite/gcc.target/riscv/rvv/base/{vadc-1.c => vmsbc-5.c} (51%) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc-8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vvm-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vvm-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vvm-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vxm_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vxm_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vxm_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vxm_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vxm_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vxm_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_tu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_tu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_tu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_tu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_tu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_tu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tumu-3.c