[Tcwg-commits] [gcc] branch master updated (142bd88c5f6 -> a75fa2518d4)

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unknown user pushed a change to branch master in repository gcc.

from 142bd88c5f6 testsuite, objective-c: Fix a testcase on Windows. new acb51b5c801 RISC-V: Add integer compare C/C++ intrinsic support new fca68b0bbf8 RISC-V: Add vmsne.vx C api tests new 946ed63e616 RISC-V: Add vmsne vv C api tests new 13a256448a5 RISC-V: Add vmslt vx C api tests new 85a8ad0a351 RISC-V: Add vmslt vv C api tests new fec15ae4a38 RISC-V: Add vmsle vx C api tests new f7b8022bcd4 RISC-V: Add vmsle vv C api tests new 6dae0aa2484 RISC-V: Add vmsgt vx C api tests new fe1a6c2c8a2 RISC-V: Add vmsgt vv C api tests new 5893cfb26a1 RISC-V: Add vmsge vx C api tests new 52ba1d2e235 RISC-V: Add vmsge vv C api tests new 76db33c592d RISC-V: Add vmseq vx C api tests new 4d06fc37909 RISC-V: Add vmseq vv C api tests new 6ec7b7b3e46 RISC-V: Add binop constraints tests for integer compare new ecdbebde7cb RISC-V: Add vmsne vx C++ tests new f87fca5d7f2 RISC-V: Add vmsne vv C++ tests new 18f4691e31e RISC-V: Add vmslt vx C++ tests new 400f003ee55 RISC-V: Add vmslt vv C++ api tests new 6c4262a5259 RISC-V: Add vmsle vx C++ api tests new d6d9206d2b6 RISC-V: Add vmsle vv C++ api tests new cfbcbe8e27b RISC-V: Add vmsgt vx C++ tests new 0d689135ffd RISC-V: Add vmsgt vv C++ tests new 92e575eacf0 RISC-V: Add vmsge vx C++ api tests new 5e96553eba9 RISC-V: Add vmsge vv C++ tests new c4e770c4521 RISC-V: Add vmseq vx C++ tests new a75fa2518d4 RISC-V: Add vmseq vv C++ tests

The 26 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.

Summary of changes: gcc/config/riscv/predicates.md | 25 +- gcc/config/riscv/riscv-v.cc | 32 +- gcc/config/riscv/riscv-vector-builtins-bases.cc | 54 ++ gcc/config/riscv/riscv-vector-builtins-bases.h | 10 + .../riscv/riscv-vector-builtins-functions.def | 20 + gcc/config/riscv/riscv-vector-builtins-shapes.cc | 2 + gcc/config/riscv/riscv-vector-builtins.cc | 77 ++ gcc/config/riscv/riscv-vector-builtins.h | 9 + gcc/config/riscv/riscv.cc | 7 +- gcc/config/riscv/riscv.md | 10 +- gcc/config/riscv/vector-iterators.md | 20 +- gcc/config/riscv/vector.md | 774 ++++++++++++++++++++- .../g++.target/riscv/rvv/base/vmseq_vv-1.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vv-2.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vv-3.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vv_m-1.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vv_m-2.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vv_m-3.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vv_mu-1.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vv_mu-2.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vv_mu-3.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vx_m_rv32-1.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vx_m_rv32-2.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vx_m_rv32-3.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vx_m_rv64-1.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vx_m_rv64-2.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vx_m_rv64-3.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vx_mu_rv32-1.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vx_mu_rv32-2.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vx_mu_rv32-3.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vx_mu_rv64-1.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vx_mu_rv64-2.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vx_mu_rv64-3.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vx_rv32-1.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vx_rv32-2.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vx_rv32-3.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vx_rv64-1.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vx_rv64-2.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vx_rv64-3.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsge_vv-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsge_vv-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsge_vv-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsge_vv_m-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsge_vv_m-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsge_vv_m-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsge_vv_mu-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsge_vv_mu-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsge_vv_mu-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsge_vx_m_rv32-1.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsge_vx_m_rv32-2.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsge_vx_m_rv32-3.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsge_vx_m_rv64-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsge_vx_m_rv64-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsge_vx_m_rv64-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsge_vx_mu_rv32-1.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsge_vx_mu_rv32-2.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsge_vx_mu_rv32-3.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsge_vx_mu_rv64-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsge_vx_mu_rv64-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsge_vx_mu_rv64-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsge_vx_rv32-1.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsge_vx_rv32-2.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsge_vx_rv32-3.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsge_vx_rv64-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsge_vx_rv64-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsge_vx_rv64-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgeu_vv-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgeu_vv-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgeu_vv-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgeu_vv_m-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgeu_vv_m-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgeu_vv_m-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgeu_vv_mu-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgeu_vv_mu-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgeu_vv_mu-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgeu_vx_m_rv32-1.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsgeu_vx_m_rv32-2.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsgeu_vx_m_rv32-3.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsgeu_vx_m_rv64-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgeu_vx_m_rv64-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgeu_vx_m_rv64-3.C | 160 +++++ .../riscv/rvv/base/vmsgeu_vx_mu_rv32-1.C | 157 +++++ .../riscv/rvv/base/vmsgeu_vx_mu_rv32-2.C | 157 +++++ .../riscv/rvv/base/vmsgeu_vx_mu_rv32-3.C | 157 +++++ .../riscv/rvv/base/vmsgeu_vx_mu_rv64-1.C | 160 +++++ .../riscv/rvv/base/vmsgeu_vx_mu_rv64-2.C | 160 +++++ .../riscv/rvv/base/vmsgeu_vx_mu_rv64-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgeu_vx_rv32-1.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsgeu_vx_rv32-2.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsgeu_vx_rv32-3.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsgeu_vx_rv64-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgeu_vx_rv64-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgeu_vx_rv64-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgt_vv-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgt_vv-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgt_vv-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgt_vv_m-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgt_vv_m-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgt_vv_m-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgt_vv_mu-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgt_vv_mu-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgt_vv_mu-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgt_vx_m_rv32-1.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsgt_vx_m_rv32-2.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsgt_vx_m_rv32-3.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsgt_vx_m_rv64-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgt_vx_m_rv64-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgt_vx_m_rv64-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgt_vx_mu_rv32-1.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsgt_vx_mu_rv32-2.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsgt_vx_mu_rv32-3.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsgt_vx_mu_rv64-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgt_vx_mu_rv64-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgt_vx_mu_rv64-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgt_vx_rv32-1.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsgt_vx_rv32-2.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsgt_vx_rv32-3.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsgt_vx_rv64-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgt_vx_rv64-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgt_vx_rv64-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgtu_vv-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgtu_vv-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgtu_vv-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgtu_vv_m-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgtu_vv_m-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgtu_vv_m-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgtu_vv_mu-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgtu_vv_mu-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgtu_vv_mu-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgtu_vx_m_rv32-1.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsgtu_vx_m_rv32-2.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsgtu_vx_m_rv32-3.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsgtu_vx_m_rv64-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgtu_vx_m_rv64-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgtu_vx_m_rv64-3.C | 160 +++++ .../riscv/rvv/base/vmsgtu_vx_mu_rv32-1.C | 157 +++++ .../riscv/rvv/base/vmsgtu_vx_mu_rv32-2.C | 157 +++++ .../riscv/rvv/base/vmsgtu_vx_mu_rv32-3.C | 157 +++++ .../riscv/rvv/base/vmsgtu_vx_mu_rv64-1.C | 160 +++++ .../riscv/rvv/base/vmsgtu_vx_mu_rv64-2.C | 160 +++++ .../riscv/rvv/base/vmsgtu_vx_mu_rv64-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgtu_vx_rv32-1.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsgtu_vx_rv32-2.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsgtu_vx_rv32-3.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsgtu_vx_rv64-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgtu_vx_rv64-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgtu_vx_rv64-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsle_vv-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsle_vv-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsle_vv-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsle_vv_m-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsle_vv_m-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsle_vv_m-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsle_vv_mu-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsle_vv_mu-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsle_vv_mu-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsle_vx_m_rv32-1.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsle_vx_m_rv32-2.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsle_vx_m_rv32-3.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsle_vx_m_rv64-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsle_vx_m_rv64-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsle_vx_m_rv64-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsle_vx_mu_rv32-1.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsle_vx_mu_rv32-2.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsle_vx_mu_rv32-3.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsle_vx_mu_rv64-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsle_vx_mu_rv64-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsle_vx_mu_rv64-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsle_vx_rv32-1.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsle_vx_rv32-2.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsle_vx_rv32-3.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsle_vx_rv64-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsle_vx_rv64-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsle_vx_rv64-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsleu_vv-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsleu_vv-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsleu_vv-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsleu_vv_m-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsleu_vv_m-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsleu_vv_m-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsleu_vv_mu-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsleu_vv_mu-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsleu_vv_mu-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsleu_vx_m_rv32-1.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsleu_vx_m_rv32-2.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsleu_vx_m_rv32-3.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsleu_vx_m_rv64-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsleu_vx_m_rv64-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsleu_vx_m_rv64-3.C | 160 +++++ .../riscv/rvv/base/vmsleu_vx_mu_rv32-1.C | 157 +++++ .../riscv/rvv/base/vmsleu_vx_mu_rv32-2.C | 157 +++++ .../riscv/rvv/base/vmsleu_vx_mu_rv32-3.C | 157 +++++ .../riscv/rvv/base/vmsleu_vx_mu_rv64-1.C | 160 +++++ .../riscv/rvv/base/vmsleu_vx_mu_rv64-2.C | 160 +++++ .../riscv/rvv/base/vmsleu_vx_mu_rv64-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsleu_vx_rv32-1.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsleu_vx_rv32-2.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsleu_vx_rv32-3.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsleu_vx_rv64-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsleu_vx_rv64-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsleu_vx_rv64-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmslt_vv-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmslt_vv-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmslt_vv-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmslt_vv_m-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmslt_vv_m-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmslt_vv_m-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmslt_vv_mu-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmslt_vv_mu-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmslt_vv_mu-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmslt_vx_m_rv32-1.C | 157 +++++ .../g++.target/riscv/rvv/base/vmslt_vx_m_rv32-2.C | 157 +++++ .../g++.target/riscv/rvv/base/vmslt_vx_m_rv32-3.C | 157 +++++ .../g++.target/riscv/rvv/base/vmslt_vx_m_rv64-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmslt_vx_m_rv64-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmslt_vx_m_rv64-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmslt_vx_mu_rv32-1.C | 157 +++++ .../g++.target/riscv/rvv/base/vmslt_vx_mu_rv32-2.C | 157 +++++ .../g++.target/riscv/rvv/base/vmslt_vx_mu_rv32-3.C | 157 +++++ .../g++.target/riscv/rvv/base/vmslt_vx_mu_rv64-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmslt_vx_mu_rv64-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmslt_vx_mu_rv64-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmslt_vx_rv32-1.C | 157 +++++ .../g++.target/riscv/rvv/base/vmslt_vx_rv32-2.C | 157 +++++ .../g++.target/riscv/rvv/base/vmslt_vx_rv32-3.C | 157 +++++ .../g++.target/riscv/rvv/base/vmslt_vx_rv64-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmslt_vx_rv64-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmslt_vx_rv64-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsltu_vv-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsltu_vv-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsltu_vv-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsltu_vv_m-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsltu_vv_m-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsltu_vv_m-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsltu_vv_mu-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsltu_vv_mu-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsltu_vv_mu-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsltu_vx_m_rv32-1.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsltu_vx_m_rv32-2.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsltu_vx_m_rv32-3.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsltu_vx_m_rv64-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsltu_vx_m_rv64-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsltu_vx_m_rv64-3.C | 160 +++++ .../riscv/rvv/base/vmsltu_vx_mu_rv32-1.C | 157 +++++ .../riscv/rvv/base/vmsltu_vx_mu_rv32-2.C | 157 +++++ .../riscv/rvv/base/vmsltu_vx_mu_rv32-3.C | 157 +++++ .../riscv/rvv/base/vmsltu_vx_mu_rv64-1.C | 160 +++++ .../riscv/rvv/base/vmsltu_vx_mu_rv64-2.C | 160 +++++ .../riscv/rvv/base/vmsltu_vx_mu_rv64-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsltu_vx_rv32-1.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsltu_vx_rv32-2.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsltu_vx_rv32-3.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsltu_vx_rv64-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsltu_vx_rv64-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsltu_vx_rv64-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsne_vv-1.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vv-2.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vv-3.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vv_m-1.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vv_m-2.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vv_m-3.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vv_mu-1.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vv_mu-2.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vv_mu-3.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vx_m_rv32-1.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vx_m_rv32-2.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vx_m_rv32-3.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vx_m_rv64-1.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vx_m_rv64-2.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vx_m_rv64-3.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vx_mu_rv32-1.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vx_mu_rv32-2.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vx_mu_rv32-3.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vx_mu_rv64-1.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vx_mu_rv64-2.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vx_mu_rv64-3.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vx_rv32-1.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vx_rv32-2.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vx_rv32-3.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vx_rv64-1.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vx_rv64-2.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vx_rv64-3.C | 292 ++++++++ .../riscv/rvv/base/binop_vv_constraint-2.c | 15 + .../riscv/rvv/base/binop_vv_constraint-3.c | 27 + .../riscv/rvv/base/binop_vv_constraint-4.c | 27 + .../riscv/rvv/base/binop_vv_constraint-5.c | 29 + .../riscv/rvv/base/binop_vv_constraint-6.c | 27 + .../riscv/rvv/base/binop_vv_constraint-7.c | 29 + .../riscv/rvv/base/binop_vx_constraint-123.c | 15 + .../riscv/rvv/base/binop_vx_constraint-124.c | 27 + .../riscv/rvv/base/binop_vx_constraint-125.c | 27 + .../riscv/rvv/base/binop_vx_constraint-126.c | 29 + .../riscv/rvv/base/binop_vx_constraint-127.c | 27 + .../riscv/rvv/base/binop_vx_constraint-128.c | 29 + .../riscv/rvv/base/binop_vx_constraint-129.c | 69 ++ .../riscv/rvv/base/binop_vx_constraint-130.c | 69 ++ .../riscv/rvv/base/binop_vx_constraint-131.c | 69 ++ .../riscv/rvv/base/binop_vx_constraint-132.c | 59 ++ .../riscv/rvv/base/binop_vx_constraint-133.c | 69 ++ .../riscv/rvv/base/binop_vx_constraint-134.c | 69 ++ .../riscv/rvv/base/binop_vx_constraint-135.c | 69 ++ .../riscv/rvv/base/binop_vx_constraint-136.c | 59 ++ .../riscv/rvv/base/binop_vx_constraint-137.c | 123 ++++ .../riscv/rvv/base/binop_vx_constraint-138.c | 123 ++++ .../riscv/rvv/base/binop_vx_constraint-139.c | 72 ++ .../riscv/rvv/base/binop_vx_constraint-140.c | 72 ++ ..._constraint-101.c => binop_vx_constraint-141.c} | 10 +- ..._constraint-101.c => binop_vx_constraint-142.c} | 10 +- ..._constraint-100.c => binop_vx_constraint-143.c} | 10 +- ..._constraint-112.c => binop_vx_constraint-144.c} | 10 +- ..._constraint-101.c => binop_vx_constraint-145.c} | 10 +- ..._constraint-113.c => binop_vx_constraint-146.c} | 10 +- .../riscv/rvv/base/binop_vx_constraint-147.c | 19 + .../riscv/rvv/base/binop_vx_constraint-148.c | 20 + .../riscv/rvv/base/binop_vx_constraint-149.c | 19 + .../riscv/rvv/base/binop_vx_constraint-150.c | 21 + .../riscv/rvv/base/binop_vx_constraint-151.c | 20 + .../riscv/rvv/base/binop_vx_constraint-152.c | 20 + .../riscv/rvv/base/binop_vx_constraint-153.c | 75 ++ .../riscv/rvv/base/binop_vx_constraint-154.c | 69 ++ .../riscv/rvv/base/binop_vx_constraint-155.c | 69 ++ .../riscv/rvv/base/binop_vx_constraint-156.c | 65 ++ .../riscv/rvv/base/binop_vx_constraint-157.c | 133 ++++ .../riscv/rvv/base/binop_vx_constraint-158.c | 69 ++ .../riscv/rvv/base/binop_vx_constraint-159.c | 65 ++ .../riscv/rvv/base/binop_vx_constraint-160.c | 133 ++++ .../riscv/rvv/base/binop_vx_constraint-161.c | 76 ++ ..._constraint-111.c => binop_vx_constraint-162.c} | 11 +- ..._constraint-100.c => binop_vx_constraint-163.c} | 10 +- ..._constraint-113.c => binop_vx_constraint-164.c} | 10 +- .../riscv/rvv/base/binop_vx_constraint-165.c | 13 + .../riscv/rvv/base/binop_vx_constraint-166.c | 15 + .../gcc.target/riscv/rvv/base/vmseq_vv-1.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vv-2.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vv-3.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vv_m-1.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vv_m-2.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vv_m-3.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vv_mu-1.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vv_mu-2.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vv_mu-3.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vx_m_rv32-1.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vx_m_rv32-2.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vx_m_rv32-3.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vx_m_rv64-1.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vx_m_rv64-2.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vx_m_rv64-3.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vx_mu_rv32-1.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vx_mu_rv32-2.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vx_mu_rv32-3.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vx_mu_rv64-1.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vx_mu_rv64-2.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vx_mu_rv64-3.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vx_rv32-1.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vx_rv32-2.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vx_rv32-3.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vx_rv64-1.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vx_rv64-2.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vx_rv64-3.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsge_vv-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsge_vv-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsge_vv-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsge_vv_m-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsge_vv_m-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsge_vv_m-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsge_vv_mu-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsge_vv_mu-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsge_vv_mu-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsge_vx_m_rv32-1.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsge_vx_m_rv32-2.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsge_vx_m_rv32-3.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsge_vx_m_rv64-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsge_vx_m_rv64-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsge_vx_m_rv64-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsge_vx_mu_rv32-1.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsge_vx_mu_rv32-2.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsge_vx_mu_rv32-3.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsge_vx_mu_rv64-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsge_vx_mu_rv64-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsge_vx_mu_rv64-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsge_vx_rv32-1.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsge_vx_rv32-2.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsge_vx_rv32-3.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsge_vx_rv64-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsge_vx_rv64-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsge_vx_rv64-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgeu_vv-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgeu_vv-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgeu_vv-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgeu_vv_m-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgeu_vv_m-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgeu_vv_m-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgeu_vv_mu-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgeu_vv_mu-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgeu_vv_mu-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv32-1.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv32-2.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv32-3.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv64-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv64-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv64-3.c | 160 +++++ .../riscv/rvv/base/vmsgeu_vx_mu_rv32-1.c | 157 +++++ .../riscv/rvv/base/vmsgeu_vx_mu_rv32-2.c | 157 +++++ .../riscv/rvv/base/vmsgeu_vx_mu_rv32-3.c | 157 +++++ .../riscv/rvv/base/vmsgeu_vx_mu_rv64-1.c | 160 +++++ .../riscv/rvv/base/vmsgeu_vx_mu_rv64-2.c | 160 +++++ .../riscv/rvv/base/vmsgeu_vx_mu_rv64-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgeu_vx_rv32-1.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsgeu_vx_rv32-2.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsgeu_vx_rv32-3.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsgeu_vx_rv64-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgeu_vx_rv64-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgeu_vx_rv64-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vv-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vv-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vv-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vv_m-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vv_m-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vv_m-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vv_mu-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vv_mu-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vv_mu-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vx_m_rv32-1.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vx_m_rv32-2.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vx_m_rv32-3.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vx_m_rv64-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vx_m_rv64-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vx_m_rv64-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv32-1.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv32-2.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv32-3.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv64-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv64-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv64-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vx_rv32-1.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vx_rv32-2.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vx_rv32-3.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vx_rv64-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vx_rv64-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vx_rv64-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgtu_vv-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgtu_vv-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgtu_vv-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgtu_vv_m-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgtu_vv_m-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgtu_vv_m-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgtu_vv_mu-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgtu_vv_mu-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgtu_vv_mu-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv32-1.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv32-2.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv32-3.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv64-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv64-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv64-3.c | 160 +++++ .../riscv/rvv/base/vmsgtu_vx_mu_rv32-1.c | 157 +++++ .../riscv/rvv/base/vmsgtu_vx_mu_rv32-2.c | 157 +++++ .../riscv/rvv/base/vmsgtu_vx_mu_rv32-3.c | 157 +++++ .../riscv/rvv/base/vmsgtu_vx_mu_rv64-1.c | 160 +++++ .../riscv/rvv/base/vmsgtu_vx_mu_rv64-2.c | 160 +++++ .../riscv/rvv/base/vmsgtu_vx_mu_rv64-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgtu_vx_rv32-1.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsgtu_vx_rv32-2.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsgtu_vx_rv32-3.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsgtu_vx_rv64-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgtu_vx_rv64-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgtu_vx_rv64-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsle_vv-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsle_vv-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsle_vv-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsle_vv_m-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsle_vv_m-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsle_vv_m-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsle_vv_mu-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsle_vv_mu-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsle_vv_mu-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsle_vx_m_rv32-1.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsle_vx_m_rv32-2.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsle_vx_m_rv32-3.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsle_vx_m_rv64-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsle_vx_m_rv64-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsle_vx_m_rv64-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsle_vx_mu_rv32-1.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsle_vx_mu_rv32-2.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsle_vx_mu_rv32-3.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsle_vx_mu_rv64-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsle_vx_mu_rv64-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsle_vx_mu_rv64-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsle_vx_rv32-1.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsle_vx_rv32-2.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsle_vx_rv32-3.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsle_vx_rv64-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsle_vx_rv64-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsle_vx_rv64-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsleu_vv-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsleu_vv-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsleu_vv-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsleu_vv_m-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsleu_vv_m-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsleu_vv_m-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsleu_vv_mu-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsleu_vv_mu-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsleu_vv_mu-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsleu_vx_m_rv32-1.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsleu_vx_m_rv32-2.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsleu_vx_m_rv32-3.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsleu_vx_m_rv64-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsleu_vx_m_rv64-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsleu_vx_m_rv64-3.c | 160 +++++ .../riscv/rvv/base/vmsleu_vx_mu_rv32-1.c | 157 +++++ .../riscv/rvv/base/vmsleu_vx_mu_rv32-2.c | 157 +++++ .../riscv/rvv/base/vmsleu_vx_mu_rv32-3.c | 157 +++++ .../riscv/rvv/base/vmsleu_vx_mu_rv64-1.c | 160 +++++ .../riscv/rvv/base/vmsleu_vx_mu_rv64-2.c | 160 +++++ .../riscv/rvv/base/vmsleu_vx_mu_rv64-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsleu_vx_rv32-1.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsleu_vx_rv32-2.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsleu_vx_rv32-3.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsleu_vx_rv64-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsleu_vx_rv64-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsleu_vx_rv64-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmslt_vv-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmslt_vv-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmslt_vv-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmslt_vv_m-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmslt_vv_m-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmslt_vv_m-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmslt_vv_mu-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmslt_vv_mu-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmslt_vv_mu-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmslt_vx_m_rv32-1.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmslt_vx_m_rv32-2.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmslt_vx_m_rv32-3.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmslt_vx_m_rv64-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmslt_vx_m_rv64-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmslt_vx_m_rv64-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmslt_vx_mu_rv32-1.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmslt_vx_mu_rv32-2.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmslt_vx_mu_rv32-3.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmslt_vx_mu_rv64-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmslt_vx_mu_rv64-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmslt_vx_mu_rv64-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmslt_vx_rv32-1.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmslt_vx_rv32-2.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmslt_vx_rv32-3.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmslt_vx_rv64-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmslt_vx_rv64-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmslt_vx_rv64-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsltu_vv-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsltu_vv-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsltu_vv-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsltu_vv_m-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsltu_vv_m-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsltu_vv_m-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsltu_vv_mu-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsltu_vv_mu-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsltu_vv_mu-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsltu_vx_m_rv32-1.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsltu_vx_m_rv32-2.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsltu_vx_m_rv32-3.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsltu_vx_m_rv64-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsltu_vx_m_rv64-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsltu_vx_m_rv64-3.c | 160 +++++ .../riscv/rvv/base/vmsltu_vx_mu_rv32-1.c | 157 +++++ .../riscv/rvv/base/vmsltu_vx_mu_rv32-2.c | 157 +++++ .../riscv/rvv/base/vmsltu_vx_mu_rv32-3.c | 157 +++++ .../riscv/rvv/base/vmsltu_vx_mu_rv64-1.c | 160 +++++ .../riscv/rvv/base/vmsltu_vx_mu_rv64-2.c | 160 +++++ .../riscv/rvv/base/vmsltu_vx_mu_rv64-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsltu_vx_rv32-1.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsltu_vx_rv32-2.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsltu_vx_rv32-3.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsltu_vx_rv64-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsltu_vx_rv64-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsltu_vx_rv64-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsne_vv-1.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vv-2.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vv-3.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vv_m-1.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vv_m-2.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vv_m-3.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vv_mu-1.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vv_mu-2.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vv_mu-3.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vx_m_rv32-1.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vx_m_rv32-2.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vx_m_rv32-3.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vx_m_rv64-1.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vx_m_rv64-2.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vx_m_rv64-3.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vx_mu_rv32-1.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vx_mu_rv32-2.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vx_mu_rv32-3.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vx_mu_rv64-1.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vx_mu_rv64-2.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vx_mu_rv64-3.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vx_rv32-1.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vx_rv32-2.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vx_rv32-3.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vx_rv64-1.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vx_rv64-2.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vx_rv64-3.c | 292 ++++++++ 602 files changed, 103292 insertions(+), 86 deletions(-) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv_m-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv_m-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv_m-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vx_m_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vx_m_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vx_m_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vx_m_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vx_m_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vx_m_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv_m-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv_m-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv_m-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vx_m_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vx_m_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vx_m_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vx_m_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vx_m_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vx_m_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vx_mu_rv64-1.C create mode 100644 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