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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_bootstrap/master-arm-bootstrap in repository toolchain/ci/gcc.
from 16f7fcadac1 RISC-V: Implement C[LT]Z_DEFINED_VALUE_AT_ZERO adds 1fe04c497d5 PR tree-optimization/83907: Improved memset handling in str [...] adds eccbd7fcee5 rs6000: Move g++.dg powerpc PR tests to g++.target adds 14e678a2c4a rs6000: Remove a few needless 'lp64' contraints. adds d75d4293dcc Improved V1TI (and V2DI) mode equality/inequality on x86_64. adds dd7813f05df compiler: always sort interface parse methods adds 62ecd2b8d46 c++: Add fixed test [PR81952] adds 9df4ffe493a Daily bump.
No new revisions were added by this update.
Summary of changes: ChangeLog | 4 + gcc/ChangeLog | 257 +++++++++++++++++ gcc/DATESTAMP | 2 +- gcc/ada/ChangeLog | 300 ++++++++++++++++++++ gcc/analyzer/ChangeLog | 4 + gcc/c-family/ChangeLog | 4 + gcc/config/i386/sse.md | 48 +++- gcc/cp/ChangeLog | 8 + gcc/fortran/ChangeLog | 6 + gcc/go/gofrontend/MERGE | 2 +- gcc/go/gofrontend/export.cc | 315 ++++++++++++++++++--- gcc/go/gofrontend/types.cc | 15 +- gcc/go/gofrontend/types.h | 9 - gcc/testsuite/ChangeLog | 147 ++++++++++ gcc/testsuite/g++.dg/overload/conv-op4.C | 22 ++ gcc/testsuite/g++.dg/pr65240-1.C | 8 - gcc/testsuite/g++.dg/pr65240-2.C | 8 - gcc/testsuite/g++.dg/pr65240-3.C | 8 - gcc/testsuite/g++.target/powerpc/pr65240-1.C | 8 + gcc/testsuite/g++.target/powerpc/pr65240-2.C | 8 + gcc/testsuite/g++.target/powerpc/pr65240-3.C | 8 + .../{g++.dg => g++.target/powerpc}/pr65240-4.C | 3 +- .../{g++.dg => g++.target/powerpc}/pr65240.h | 0 .../{g++.dg => g++.target/powerpc}/pr65242.C | 3 +- .../{g++.dg => g++.target/powerpc}/pr67211.C | 3 +- .../{g++.dg => g++.target/powerpc}/pr69667.C | 3 +- .../{g++.dg => g++.target/powerpc}/pr71294.C | 1 - .../{g++.dg => g++.target/powerpc}/pr84264.C | 2 +- .../{g++.dg => g++.target/powerpc}/pr84279.C | 4 +- .../{g++.dg => g++.target/powerpc}/pr85657.C | 2 +- .../{g++.dg => g++.target/powerpc}/pr93974.C | 0 gcc/testsuite/gcc.dg/tree-ssa/pr83907-1.c | 13 + gcc/testsuite/gcc.dg/tree-ssa/pr83907-2.c | 14 + gcc/testsuite/gcc.target/i386/sse2-v1ti-veq.c | 12 + gcc/testsuite/gcc.target/i386/sse2-v1ti-vne.c | 13 + gcc/tree-ssa-strlen.cc | 48 +++- libgcc/ChangeLog | 6 + libgomp/ChangeLog | 16 ++ libstdc++-v3/ChangeLog | 121 ++++++++ 39 files changed, 1357 insertions(+), 98 deletions(-) create mode 100644 gcc/testsuite/g++.dg/overload/conv-op4.C delete mode 100644 gcc/testsuite/g++.dg/pr65240-1.C delete mode 100644 gcc/testsuite/g++.dg/pr65240-2.C delete mode 100644 gcc/testsuite/g++.dg/pr65240-3.C create mode 100644 gcc/testsuite/g++.target/powerpc/pr65240-1.C create mode 100644 gcc/testsuite/g++.target/powerpc/pr65240-2.C create mode 100644 gcc/testsuite/g++.target/powerpc/pr65240-3.C rename gcc/testsuite/{g++.dg => g++.target/powerpc}/pr65240-4.C (68%) rename gcc/testsuite/{g++.dg => g++.target/powerpc}/pr65240.h (100%) rename gcc/testsuite/{g++.dg => g++.target/powerpc}/pr65242.C (93%) rename gcc/testsuite/{g++.dg => g++.target/powerpc}/pr67211.C (91%) rename gcc/testsuite/{g++.dg => g++.target/powerpc}/pr69667.C (97%) rename gcc/testsuite/{g++.dg => g++.target/powerpc}/pr71294.C (96%) rename gcc/testsuite/{g++.dg => g++.target/powerpc}/pr84264.C (79%) rename gcc/testsuite/{g++.dg => g++.target/powerpc}/pr84279.C (90%) rename gcc/testsuite/{g++.dg => g++.target/powerpc}/pr85657.C (90%) rename gcc/testsuite/{g++.dg => g++.target/powerpc}/pr93974.C (100%) create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr83907-1.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr83907-2.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-v1ti-veq.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-v1ti-vne.c