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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-arm-stable-defconfig in repository toolchain/ci/qemu.
from 2c89b5af5e Merge remote-tracking branch 'remotes/pmaydell/tags/pull-tar [...] adds 28ca4689ae hw: timer: ibex_timer: Fixup reading w/o register adds 0df470c388 riscv: opentitan: fixup plic stride len adds dda94e5c66 hw: timer: ibex_timer: update/add reg address adds b91a0fa70c update-linux-headers: Add asm-riscv/kvm.h adds 91654e613b target/riscv: Add target/riscv/kvm.c to place the public kvm [...] adds 0a312b85cb target/riscv: Implement function kvm_arch_init_vcpu adds 937f0b4512 target/riscv: Implement kvm_arch_get_registers adds 9997cc1e19 target/riscv: Implement kvm_arch_put_registers adds ad40be2708 target/riscv: Support start kernel directly by KVM adds 2b650fbbcc target/riscv: Support setting external interrupt by KVM adds 4eb471258b target/riscv: Handle KVM_EXIT_RISCV_SBI exit adds 10f1ca27e0 target/riscv: Add host cpu type adds 27abe66f31 target/riscv: Add kvm_riscv_get/put_regs_timer adds 9ad3e016ae target/riscv: Implement virtual time adjusting with vm state [...] adds 1eb9a5da31 target/riscv: Support virtual time context synchronization adds fbf43c7dbf target/riscv: enable riscv kvm accel adds cfeeeb482a softmmu/device_tree: Silence compiler warning with --enable- [...] adds 22599b795c softmmu/device_tree: Remove redundant pointer assignment adds b4a99d4027 target/riscv: rvv-1.0: Add Zve64f extension into RISC-V adds c7a26fb2f6 target/riscv: rvv-1.0: Add Zve64f support for configuration insns adds 494104093f target/riscv: rvv-1.0: Add Zve64f support for load and store insns adds aaae69942f target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns adds 13dbc826fd target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and v [...] adds 40d78c85f6 target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns adds 193fb5c9bd target/riscv: rvv-1.0: Add Zve64f support for single-width f [...] adds 235d1161d4 target/riscv: rvv-1.0: Add Zve64f support for widening type- [...] adds 68fa38970e target/riscv: rvv-1.0: Add Zve64f support for narrowing type [...] adds bfefe406b7 target/riscv: rvv-1.0: Allow Zve64f extension to be turned on adds 32e579b8c5 target/riscv: rvv-1.0: Add Zve32f extension into RISC-V adds da61f1256f target/riscv: rvv-1.0: Add Zve32f support for configuration insns adds abe2d74032 target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns adds 8527b5db72 target/riscv: rvv-1.0: Add Zve32f support for single-width f [...] adds f4dcf51cdc target/riscv: rvv-1.0: Add Zve32f support for widening type- [...] adds 6db02328a7 target/riscv: rvv-1.0: Add Zve32f support for narrowing type [...] adds 2fc1b44dd0 target/riscv: rvv-1.0: Allow Zve32f extension to be turned on adds 8d8897accb hw/riscv: spike: Allow using binary firmware as bios adds 092dc6df92 hw/riscv: Remove macros for ELF BIOS image names adds 4211fc5532 roms/opensbi: Remove ELF images adds 79f26b3b95 target/riscv: Adjust pmpcfg access with mxl adds b655dc7cd9 target/riscv: Don't save pc when exception return adds a14db52f7f target/riscv: Sign extend link reg for jal and jalr adds 40f0c2046c target/riscv: Sign extend pc for different XLEN adds 440544e1cf target/riscv: Create xl field in env adds 8c796f1a15 target/riscv: Ignore the pc bits above XLEN adds bf9e776ec1 target/riscv: Extend pc for runtime pc write adds 1191be09a9 target/riscv: Use gdb xml according to max mxlen adds 47bdec821b target/riscv: Relax debug check for pm write adds 83b519b8a4 target/riscv: Adjust csr write mask with XLEN adds 40bfa5f695 target/riscv: Create current pm fields in env adds 0cff460de9 target/riscv: Alloc tcg global for cur_pm[mask|base] adds 4302bef9e1 target/riscv: Calculate address according to XLEN adds 4208dc7e9e target/riscv: Split pm_enabled into mask and base adds d96a271a8d target/riscv: Split out the vill from vtype adds 31961cfe50 target/riscv: Adjust vsetvl according to XLEN adds eef11ce325 target/riscv: Remove VILL field in VTYPE adds 01d09525da target/riscv: Fix check range for first fault only adds d6b9d93023 target/riscv: Adjust vector address with mask adds d8c40c24fd target/riscv: Adjust scalar reg in vector with XLEN adds 5a2ae2350e target/riscv: Set default XLEN for hypervisor adds f310df58bd target/riscv: Enable uxl field write adds f297245f6a target/riscv: Relax UXL field for debugging adds 5e9d14f2be Merge remote-tracking branch 'remotes/alistair/tags/pull-ris [...] adds 1e4d8b31be python: pin setuptools below v60.0.0 adds 57a6b4478c python: use avocado's "new" runner adds dc6877bd2e python/aqmp: fix docstring typo adds 3bc72e3aed python/aqmp: add __del__ method to legacy interface adds 3b5bf136f5 python/aqmp: handle asyncio.TimeoutError on execute() adds 0e6bfd8b96 python/aqmp: copy type definitions from qmp adds 728dcac5e3 python/aqmp: add SocketAddrT to package root adds 6e7751dc38 python/aqmp: rename AQMPError to QMPError adds 7017f3853a python/qemu-ga-client: don't use deprecated CLI syntax in us [...] adds 26db07516f python/qmp: switch qemu-ga-client to AQMP adds 8d6cdc5118 python/qmp: switch qom tools to AQMP adds f3efd12930 python/qmp: switch qmp-shell to AQMP adds 0347c4c4cf python: move qmp utilities to python/qemu/utils adds fd9c3a6219 python: move qmp-shell under the AQMP package adds 9922125615 scripts/cpu-x86-uarch-abi: fix CLI parsing adds 0665410dcf scripts/cpu-x86-uarch-abi: switch to AQMP adds 0590860242 scripts/render-block-graph: switch to AQMP adds aeb0ae95b7 Merge remote-tracking branch 'remotes/jsnow-gitlab/tags/pyth [...]
No new revisions were added by this update.
Summary of changes: .gitlab-ci.d/opensbi.yml | 2 - hw/char/riscv_htif.c | 33 +- hw/intc/sifive_plic.c | 20 +- hw/riscv/boot.c | 16 +- hw/riscv/opentitan.c | 2 +- hw/riscv/spike.c | 45 ++- hw/riscv/virt.c | 83 ++-- hw/timer/ibex_timer.c | 25 +- include/hw/char/riscv_htif.h | 5 +- include/hw/riscv/boot.h | 3 +- include/hw/riscv/spike.h | 1 + include/hw/timer/ibex_timer.h | 1 - linux-headers/asm-riscv/kvm.h | 128 ++++++ meson.build | 2 + pc-bios/meson.build | 2 - pc-bios/opensbi-riscv32-generic-fw_dynamic.elf | Bin 838904 -> 0 bytes pc-bios/opensbi-riscv64-generic-fw_dynamic.elf | Bin 934696 -> 0 bytes python/Makefile | 2 + python/README.rst | 2 +- python/avocado.cfg | 2 +- python/qemu/aqmp/__init__.py | 16 +- python/qemu/aqmp/error.py | 12 +- python/qemu/aqmp/events.py | 4 +- python/qemu/aqmp/legacy.py | 41 +- python/qemu/aqmp/protocol.py | 24 +- python/qemu/aqmp/qmp_client.py | 16 +- python/qemu/{qmp => aqmp}/qmp_shell.py | 31 +- python/qemu/{qmp => utils}/qemu_ga_client.py | 24 +- python/qemu/{qmp => utils}/qom.py | 5 +- python/qemu/{qmp => utils}/qom_common.py | 3 +- python/qemu/{qmp => utils}/qom_fuse.py | 11 +- python/setup.cfg | 19 +- roms/Makefile | 2 - scripts/cpu-x86-uarch-abi.py | 7 +- scripts/qmp/qemu-ga-client | 2 +- scripts/qmp/qmp-shell | 2 +- scripts/qmp/qom-fuse | 2 +- scripts/qmp/qom-get | 2 +- scripts/qmp/qom-list | 2 +- scripts/qmp/qom-set | 2 +- scripts/qmp/qom-tree | 2 +- scripts/render_block_graph.py | 8 +- softmmu/device_tree.c | 11 +- target/riscv/cpu.c | 77 +++- target/riscv/cpu.h | 58 ++- target/riscv/cpu_bits.h | 3 + target/riscv/cpu_helper.c | 99 ++--- target/riscv/csr.c | 90 ++++- target/riscv/gdbstub.c | 71 +++- target/riscv/helper.h | 4 +- target/riscv/insn_trans/trans_privileged.c.inc | 9 +- target/riscv/insn_trans/trans_rva.c.inc | 9 +- target/riscv/insn_trans/trans_rvd.c.inc | 19 +- target/riscv/insn_trans/trans_rvf.c.inc | 19 +- target/riscv/insn_trans/trans_rvi.c.inc | 39 +- target/riscv/insn_trans/trans_rvv.c.inc | 225 +++++++++-- target/{rx/cpu-param.h => riscv/kvm-stub.c} | 26 +- target/riscv/kvm.c | 535 +++++++++++++++++++++++++ target/{rx/cpu-param.h => riscv/kvm_riscv.h} | 17 +- target/riscv/machine.c | 46 ++- target/riscv/meson.build | 1 + target/riscv/op_helper.c | 7 +- target/riscv/pmp.c | 12 +- target/riscv/sbi_ecall_interface.h | 72 ++++ target/riscv/translate.c | 94 +++-- target/riscv/vector_helper.c | 39 +- 66 files changed, 1723 insertions(+), 470 deletions(-) create mode 100644 linux-headers/asm-riscv/kvm.h delete mode 100644 pc-bios/opensbi-riscv32-generic-fw_dynamic.elf delete mode 100644 pc-bios/opensbi-riscv64-generic-fw_dynamic.elf rename python/qemu/{qmp => aqmp}/qmp_shell.py (96%) rename python/qemu/{qmp => utils}/qemu_ga_client.py (94%) rename python/qemu/{qmp => utils}/qom.py (98%) rename python/qemu/{qmp => utils}/qom_common.py (98%) rename python/qemu/{qmp => utils}/qom_fuse.py (97%) copy target/{rx/cpu-param.h => riscv/kvm-stub.c} (67%) create mode 100644 target/riscv/kvm.c copy target/{rx/cpu-param.h => riscv/kvm_riscv.h} (70%) create mode 100644 target/riscv/sbi_ecall_interface.h