[Tcwg-commits] [gcc] branch master updated (7accc6208be -> a248e1cc860)

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from 7accc6208be RISC-V: Make sure we get VL REG operand for VLMAX vsetvl new a248e1cc860 RISC-V: Make arch-24.c to test "success" case

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Summary of changes: gcc/testsuite/gcc.target/riscv/arch-24.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-)