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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_llvm_apm/llvm-master-aarch64-spec2k6-Os in repository toolchain/ci/llvm-project.
from dae7adda9499 [AVR][clang] Pass '-fno-use-init-array' to cc1 as default adds 4d3d182c1dcb Revert "[LLDB][GUI] Refactor form drawing using subsurfaces" adds 28939b6ae5de [NFC] Clean up and clang-format openmp/libomptarget/plugin [...] adds 43018f03ed18 [PowerPC] Pre-commit test for D107428. NFC. adds 7138f1cd13d3 [NFC][sanitizer] clang-format sem related block adds 9d10be70a828 [mlir] std.call reference function return types in failure adds 6f84d94b9c56 [PowerPC] Fix copy/paste error in scalar_to_vector patterns adds ac42f7609027 [libc++] s/_VSTD::_IsSame/_IsSame/. NFCI. adds 7ece20505f12 [Lanai] fix lowering wide returns adds daab81cda18a Replace "CHECK-NOT: #{{.*}}" with same-line positive checks. NFC. adds a1b21ed3fb4a [GCov] Emit memset instead of stores in __llvm_gcov_reset adds ab737d5367cd [fuzzer] Fix building on case sensitive mingw platforms adds 666ee849f077 [PowerPC] Fix shift amount of xxsldwi when performing vect [...] adds 4fee756c75af Delete copy-ctor of MachineFrameInfo. adds d6b4993736c2 [mlir][MemRef] Fix canonicalization of BufferCast(TensorLoad). adds dc9b41f3b45f [JITLink][RISCV] Add relocation fixup test adds 82ca845b4793 [NFC] [FuncSpec] Update the Todo list for recursive functions adds 4b8806d95769 [doc] added links to discord and discourse adds 2d9af3db79e6 [GlobalISel] Make GLoadStore::getMemSize[InBits]() const. adds 835cbfa8cf63 [mlir][python] Make a number of imports relative. adds 3e58dd19dfa3 [LV] Move reduction PHI node fixup to VPlan::execute (NFC). adds 4c4093e6e39f Introduce intrinsic llvm.isnan adds cc3f40bb41a7 [FuncSpec] Move invariant computation for spec cost out of [...] adds 62fc3e0ad6e4 [NFC] [FuncSpec] Remove unused variables in isArgumentInteresting adds cd2594e1c678 [GlobalISel] Improve legalization of narrow CTTZ adds d77b43c38527 [AMDGPU][GlobalISel] Add G_AMDGPU_FFBL_B32 adds 24b67a9024cc [AMDGPU][GlobalISel] Improve regbankselect for 64-bit VGPR [...] adds 83610d4eb025 [AMDGPU][GlobalISel] Better legalization of 32-bit ctlz/cttz adds 43a5c750d183 Revert "[LoopVectorize] Add support for replication of mor [...] adds 2919ac897172 [llvm-readobj][XCOFF] Warn about invalid offset adds 0fd03feb4ba5 [FuncSpec] Return changed if function is changed by tryToR [...] adds 59f59d1c621c [mlir] Allow to override type/attr aliases from various hooks adds 3fd96e1b2e12 [LoopVectorize] Improve vectorisation of some intrinsics b [...] adds 22fdf617b610 [OpenCL][Docs] Adding builtins requires adding to both now adds 08bc4411740b [AArch64] NFC: drop unnecessary llvm:: namespace prefix on MCInst adds 9c63e5b415d1 [Orc][examples] Temporarily disable tests for the C API du [...] adds a5a2f05dcc80 [C++4OpenCL] Introduces __remove_address_space utility adds aa2210a83069 [linalg] Expose `rewriteAsPaddedOp` function. adds 18e6a03b1a15 [X86][AVX] Extract SUBV_BROADCAST constant bits from just [...] adds dbce6a8d9d7c [ARM] Fold insert_subvector to concat_vectors adds 5173854f1994 [AMDGPU] Handle functions in llvm's global ctors and dtors list adds 6385abd0c449 Split 'qualifier on reference type has no effect' out into [...] adds ae1a2a09e41e [NFC][MLGO] Make logging more robust adds 779714f89bef [profile] Only use NT_GNU_BUILD_ID if supported adds 3709822d2602 [flang][docs] Document the `flang` wrapper script adds 4aafd5f00c2a [clang] Remove misleading assertion in FullSourceLoc
No new revisions were added by this update.
Summary of changes: clang/docs/LanguageExtensions.rst | 24 + clang/docs/OpenCLSupport.rst | 2 +- clang/include/clang/Basic/DiagnosticGroups.td | 3 +- clang/include/clang/Basic/DiagnosticSemaKinds.td | 2 +- clang/include/clang/Basic/SourceLocation.h | 13 +- clang/lib/CodeGen/CGBuiltin.cpp | 28 +- clang/lib/Headers/opencl-c-base.h | 20 + clang/test/CodeGen/X86/strictfp_builtins.c | 37 +- clang/test/CodeGen/aarch64-strictfp-builtins.c | 38 +- clang/test/CodeGen/strictfp_builtins.c | 152 +- .../CodeGenOpenCLCXX/remove-address-space.clcpp | 34 + clang/test/Modules/Inputs/explicit-build-diags/a.h | 1 + .../module.modulemap | 0 clang/test/Modules/explicit-build-diags.cpp | 8 + .../lib/fuzzer/FuzzerExtraCountersWindows.cpp | 2 +- .../lib/profile/InstrProfilingPlatformLinux.c | 10 + .../sanitizer_common_interceptors.inc | 22 +- flang/docs/FlangDriver.md | 27 + libcxx/include/concepts | 2 +- lldb/source/Core/IOHandlerCursesGUI.cpp | 91 +- llvm/docs/AMDGPUUsage.rst | 31 + llvm/docs/GettingInvolved.rst | 9 +- llvm/docs/LangRef.rst | 46 + llvm/include/llvm/Analysis/Utils/TFUtils.h | 7 +- .../llvm/CodeGen/GlobalISel/GenericMachineInstrs.h | 4 +- llvm/include/llvm/CodeGen/ISDOpcodes.h | 4 + llvm/include/llvm/CodeGen/MachineFrameInfo.h | 2 + llvm/include/llvm/CodeGen/TargetLowering.h | 4 + llvm/include/llvm/IR/Intrinsics.td | 8 + llvm/lib/Analysis/ConstantFolding.cpp | 6 +- llvm/lib/Analysis/DevelopmentModeInlineAdvisor.cpp | 2 +- llvm/lib/Analysis/TFUtils.cpp | 75 +- llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 7 +- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 10 + .../CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp | 10 + llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h | 4 + .../CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 63 + .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 24 + .../CodeGen/SelectionDAG/SelectionDAGDumper.cpp | 1 + llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 29 + llvm/lib/CodeGen/TargetLoweringBase.cpp | 1 + .../AArch64/Disassembler/AArch64Disassembler.cpp | 18 +- llvm/lib/Target/AMDGPU/AMDGPU.h | 4 + llvm/lib/Target/AMDGPU/AMDGPUCtorDtorLowering.cpp | 95 + llvm/lib/Target/AMDGPU/AMDGPUGISel.td | 1 + .../Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp | 4 + llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 26 +- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h | 2 + llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 57 +- llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 2 + llvm/lib/Target/AMDGPU/CMakeLists.txt | 1 + llvm/lib/Target/AMDGPU/SIInstructions.td | 8 + llvm/lib/Target/ARM/ARMISelLowering.cpp | 43 + llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp | 2 +- llvm/lib/Target/Lanai/LanaiISelLowering.cpp | 9 + llvm/lib/Target/Lanai/LanaiISelLowering.h | 5 + llvm/lib/Target/PowerPC/PPCInstrVSX.td | 6 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 55 +- llvm/lib/Transforms/IPO/FunctionSpecialization.cpp | 42 +- .../Transforms/InstCombine/InstCombineCalls.cpp | 12 + .../Transforms/Instrumentation/GCOVProfiling.cpp | 8 +- llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 21 +- llvm/lib/Transforms/Vectorize/VPlan.cpp | 28 +- llvm/test/Assembler/2008-09-02-FunctionNotes.ll | 7 +- llvm/test/CodeGen/AArch64/aarch64-fpclass.ll | 490 +++++ .../CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll | 25 +- .../GlobalISel/inst-select-amdgpu-ffbl-b32.mir | 68 + .../CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir | 129 +- .../CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir | 106 +- .../CodeGen/AMDGPU/GlobalISel/legalize-uitofp.mir | 150 +- .../GlobalISel/regbankselect-amdgpu-ffbh-u32.mir | 3 +- ...h-u32.mir => regbankselect-amdgpu-ffbl-b32.mir} | 17 +- .../GlobalISel/regbankselect-ctlz-zero-undef.mir | 14 +- .../GlobalISel/regbankselect-cttz-zero-undef.mir | 14 +- llvm/test/CodeGen/AMDGPU/ctlz.ll | 129 +- llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll | 18 +- llvm/test/CodeGen/AMDGPU/cttz.ll | 103 +- llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll | 23 +- .../hsa-metadata-from-llvm-ctor-dtor-list.ll | 39 + llvm/test/CodeGen/AMDGPU/llc-pipeline.ll | 5 + llvm/test/CodeGen/AMDGPU/lower-ctor-dtor.ll | 21 + .../CodeGen/AMDGPU/lower-multiple-ctor-dtor.ll | 31 + llvm/test/CodeGen/ARM/neon-copy.ll | 2095 ++++++++++++++++++++ llvm/test/CodeGen/Lanai/lowering-128.ll | 13 + llvm/test/CodeGen/PowerPC/build-vector-tests.ll | 8 +- llvm/test/CodeGen/PowerPC/ppc-fpclass.ll | 535 +++++ llvm/test/CodeGen/PowerPC/scalar_vector_test_5.ll | 2 +- .../CodeGen/PowerPC/vec_int_to_double_shuffle.ll | 39 + llvm/test/CodeGen/X86/pr51281.ll | 4 +- llvm/test/CodeGen/X86/x86-fpclass.ll | 1098 ++++++++++ llvm/test/Examples/lit.local.cfg | 10 + .../ExecutionEngine/JITLink/RISCV/ELF_abs_reloc.s | 33 + .../JITLink/RISCV/ELF_pc_indirect.s | 24 +- .../function-specialization-constant-expression.ll | 49 + llvm/test/Transforms/GCOVProfiling/reset.ll | 37 + .../test/Transforms/InferFunctionAttrs/annotate.ll | 19 +- llvm/test/Transforms/InstCombine/fpclass.ll | 73 + .../InstSimplify/ConstProp/fpclassify.ll | 35 + llvm/tools/llvm-readobj/ObjDumper.cpp | 10 +- llvm/unittests/Analysis/TFUtilsTest.cpp | 8 +- .../CodeGen/GlobalISel/LegalizerHelperTest.cpp | 2 +- .../gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn | 1 + .../mlir/Dialect/Linalg/Transforms/Transforms.h | 7 + mlir/include/mlir/IR/OpImplementation.h | 23 +- mlir/lib/Dialect/Linalg/Transforms/Transforms.cpp | 42 +- mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp | 48 +- mlir/lib/Dialect/StandardOps/IR/Ops.cpp | 8 +- mlir/lib/IR/AsmPrinter.cpp | 31 +- mlir/lib/IR/BuiltinDialect.cpp | 16 +- .../mlir/dialects/linalg/opdsl/lang/affine.py | 2 +- .../dialects/linalg/opdsl/lang/comprehension.py | 3 +- .../mlir/dialects/linalg/opdsl/lang/config.py | 3 +- mlir/python/mlir/dialects/linalg/opdsl/lang/dsl.py | 2 +- .../mlir/dialects/linalg/opdsl/lang/emitter.py | 8 +- mlir/test/Dialect/MemRef/canonicalize.mlir | 35 +- mlir/test/Dialect/Standard/invalid.mlir | 16 + mlir/test/IR/print-attr-type-aliases.mlir | 3 + mlir/test/lib/Dialect/Test/TestDialect.cpp | 21 +- openmp/libomptarget/plugins/cuda/src/rtl.cpp | 84 +- 119 files changed, 6268 insertions(+), 883 deletions(-) create mode 100644 clang/test/CodeGenOpenCLCXX/remove-address-space.clcpp create mode 100644 clang/test/Modules/Inputs/explicit-build-diags/a.h copy clang/test/Modules/Inputs/{static_assert => explicit-build-diags}/module.modu [...] create mode 100644 clang/test/Modules/explicit-build-diags.cpp create mode 100644 llvm/lib/Target/AMDGPU/AMDGPUCtorDtorLowering.cpp create mode 100644 llvm/test/CodeGen/AArch64/aarch64-fpclass.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbl-b32.mir copy llvm/test/CodeGen/AMDGPU/GlobalISel/{regbankselect-amdgpu-ffbh-u32.mir => reg [...] create mode 100644 llvm/test/CodeGen/AMDGPU/hsa-metadata-from-llvm-ctor-dtor-list.ll create mode 100644 llvm/test/CodeGen/AMDGPU/lower-ctor-dtor.ll create mode 100644 llvm/test/CodeGen/AMDGPU/lower-multiple-ctor-dtor.ll create mode 100644 llvm/test/CodeGen/ARM/neon-copy.ll create mode 100644 llvm/test/CodeGen/Lanai/lowering-128.ll create mode 100644 llvm/test/CodeGen/PowerPC/ppc-fpclass.ll create mode 100644 llvm/test/CodeGen/PowerPC/vec_int_to_double_shuffle.ll create mode 100644 llvm/test/CodeGen/X86/x86-fpclass.ll create mode 100644 llvm/test/ExecutionEngine/JITLink/RISCV/ELF_abs_reloc.s create mode 100644 llvm/test/Transforms/FunctionSpecialization/function-specializa [...] create mode 100644 llvm/test/Transforms/GCOVProfiling/reset.ll create mode 100644 llvm/test/Transforms/InstCombine/fpclass.ll create mode 100644 llvm/test/Transforms/InstSimplify/ConstProp/fpclassify.ll