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from 6ba4049f7df AMDGPU/GlobalISel: Split VALU s64 G_ZEXT/G_SEXT in RegBankSelect new 85cf93877df [PowerPC][UpdateTestChecks] powerpc- triple support new 0bb983e6aec AMDGPU/GlobalISel: RegBankSelect for amdgcn.class new d73371c16ba AMDGPU/GlobalISel: Select G_TRUNC
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Summary of changes: lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp | 72 ++++ lib/Target/AMDGPU/AMDGPUInstructionSelector.h | 1 + lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 9 + lib/Target/AMDGPU/SIRegisterInfo.cpp | 54 +-- lib/Target/AMDGPU/SIRegisterInfo.h | 12 + .../AMDGPU/GlobalISel/inst-select-trunc.mir | 373 +++++++++++++++++++++ ...ct-fexp2.mir => regbankselect-amdgcn.class.mir} | 16 +- test/CodeGen/PowerPC/varargs.ll | 63 ++-- utils/UpdateTestChecks/asm.py | 3 +- 9 files changed, 539 insertions(+), 64 deletions(-) create mode 100644 test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.mir copy test/CodeGen/AMDGPU/GlobalISel/{regbankselect-fexp2.mir => regbankselect-amdg [...]