[Tcwg-commits] [llvm] branch master updated (7e9b796 -> 7b27dc2)

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from 7e9b796 [X86] Enable RRL part of the LEA optimization pass for -O2. new 7b27dc2 [mips][mips16] Fix ZERO is not a CPU16Regs register error fro [...]

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Summary of changes: lib/Target/Mips/Mips16InstrInfo.td | 2 +- test/CodeGen/Mips/mips16fpe.ll | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-)