This is an automated email from the git hooks/post-receive script.
unknown user pushed a change to branch master in repository gcc.
from d5c58ad1eba libgomp/testsuite: Add requires-unified-addr-1.{c,f90} [PR109837] new 1d4d302acd9 RISC-V: Add vector psabi checking.
The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.
Summary of changes: gcc/config/riscv/riscv-protos.h | 2 + gcc/config/riscv/riscv.cc | 112 ++++++++++++++++++++- gcc/config/riscv/riscv.h | 5 +- gcc/testsuite/g++.target/riscv/rvv/base/pr109244.C | 2 +- gcc/testsuite/g++.target/riscv/rvv/base/pr109535.C | 2 +- .../riscv/rvv/base/binop_vx_constraint-120.c | 2 +- .../riscv/rvv/base/integer_compare_insn_shortcut.c | 2 +- .../gcc.target/riscv/rvv/base/mask_insn_shortcut.c | 2 +- .../riscv/rvv/base/misc_vreinterpret_vbool_vint.c | 2 +- .../gcc.target/riscv/rvv/base/pr110109-2.c | 2 +- .../gcc.target/riscv/rvv/base/scalar_move-9.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c | 2 +- .../gcc.target/riscv/rvv/base/vlmul_ext-1.c | 2 +- .../rvv/base/zero_base_load_store_optimization.c | 2 +- .../gcc.target/riscv/rvv/base/zvfh-intrinsic.c | 2 +- .../gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c | 2 +- .../gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-1.c | 2 +- gcc/testsuite/gcc.target/riscv/vector-abi-1.c | 14 +++ gcc/testsuite/gcc.target/riscv/vector-abi-2.c | 15 +++ gcc/testsuite/gcc.target/riscv/vector-abi-3.c | 14 +++ gcc/testsuite/gcc.target/riscv/vector-abi-4.c | 16 +++ gcc/testsuite/gcc.target/riscv/vector-abi-5.c | 15 +++ gcc/testsuite/gcc.target/riscv/vector-abi-6.c | 20 ++++ 26 files changed, 228 insertions(+), 19 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-6.c