[Tcwg-commits] [gcc] branch master updated (6e85f89a7d5 -> 8577356f4b8)

19 Dec 2022


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unknown user pushed a change to branch master
in repository gcc.
from  6e85f89a7d5 testsuite: Fix up pr64536.c for LLP64 targets [PR108151]
       new  22dc669e109 RISC-V: Fix RVV machine mode attribute configuration
       new  9243c3d1b63 RISC-V: Support VSETVL PASS for RVV support
       new  c2c29fbebb9 RISC-V: Simplify ASM checks in gcc.target/riscv/rvv/base/.
       new  e4433e075fc RISC-V: Add testcases for VSETVL PASS
       new  6f18836ca03 RISC-V: Add testcases for VSETVL PASS 2
       new  76023293e6e RISC-V: Add testcases for VSETVL PASS 3
       new  5a1b66b77cf RISC-V: Add testcases for VSETVL PASS 4
       new  6c098f7d23d RISC-V: Add testcases for VSETVL PASS 5
       new  8577356f4b8 RISC-V: Remove unit-stride store from ta attribute
The 9 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails.  The revisions
listed as "adds" were already present in the repository and have only
been added to this reference.
Summary of changes:
 gcc/config.gcc                                     |    2 +-
 gcc/config/riscv/riscv-passes.def                  |    1 +
 gcc/config/riscv/riscv-protos.h                    |   15 +
 gcc/config/riscv/riscv-v.cc                        |  102 +-
 gcc/config/riscv/riscv-vector-switch.def           |   38 +-
 gcc/config/riscv/riscv-vsetvl.cc                   | 2509 ++++++++++++++++++++
 gcc/config/riscv/riscv-vsetvl.h                    |  344 +++
 gcc/config/riscv/t-riscv                           |    8 +
 gcc/config/riscv/vector.md                         |  131 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/mov-1.c    |   68 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/mov-10.c   |   56 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/mov-11.c   |   56 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/mov-12.c   |   20 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/mov-2.c    |   56 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/mov-3.c    |   44 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/mov-4.c    |   32 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/mov-5.c    |   22 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/mov-6.c    |   16 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/mov-8.c    |   42 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/mov-9.c    |   24 +-
 .../gcc.target/riscv/rvv/base/vread_csr.c          |    8 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c |  176 +-
 .../gcc.target/riscv/rvv/base/vwrite_csr.c         |    8 +-
 gcc/testsuite/gcc.target/riscv/rvv/rvv.exp         |    2 +
 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/dump-1.c |   33 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-1.c           |   36 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-10.c          |   59 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-11.c          |   63 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-12.c          |   64 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-13.c          |   64 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-14.c          |   58 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-15.c          |  143 ++
 .../riscv/rvv/vsetvl/vlmax_back_prop-16.c          |   54 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-17.c          |   59 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-18.c          |   58 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-19.c          |   48 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-2.c           |   50 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-20.c          |   59 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-21.c          |   50 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-22.c          |   58 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-23.c          |   41 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-24.c          |   41 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-25.c          |   96 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-26.c          |   89 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-27.c          |   51 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-28.c          |   54 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-29.c          |   54 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-3.c           |   47 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-30.c          |   44 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-31.c          |   46 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-32.c          |   46 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-33.c          |   45 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-34.c          |   45 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-35.c          |   38 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-36.c          |   47 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-37.c          |   41 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-38.c          |   73 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-39.c          |   20 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-4.c           |  104 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-40.c          |   22 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-41.c          |   26 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-42.c          |   26 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-43.c          |   27 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-44.c          |   28 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-45.c          |   34 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-46.c          |   32 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-5.c           |   48 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-6.c           |  155 ++
 .../riscv/rvv/vsetvl/vlmax_back_prop-7.c           |   43 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-8.c           |  149 ++
 .../riscv/rvv/vsetvl/vlmax_back_prop-9.c           |   44 +
 .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-1.c  |  182 ++
 .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c |  230 ++
 .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c |   43 +
 .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c |  266 +++
 .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-13.c |  221 ++
 .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-14.c |  221 ++
 .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-15.c |   41 +
 .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-16.c |  257 ++
 .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c |  177 ++
 .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c |  177 ++
 .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c |   34 +
 .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-2.c  |  182 ++
 .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c |  203 ++
 .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-21.c |  155 ++
 .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-22.c |  155 ++
 .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-23.c |   30 +
 .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-24.c |  180 ++
 .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-25.c |  572 +++++
 .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-26.c |  492 ++++
 .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-27.c |  491 ++++
 .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-28.c |   86 +
 .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c  |   35 +
 .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-4.c  |  210 ++
 .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-5.c  |  167 ++
 .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-6.c  |  167 ++
 .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-7.c  |   32 +
 .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-8.c  |  194 ++
 .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c  |  230 ++
 .../gcc.target/riscv/rvv/vsetvl/vlmax_call-1.c     |  239 ++
 .../gcc.target/riscv/rvv/vsetvl/vlmax_call-2.c     |  207 ++
 .../gcc.target/riscv/rvv/vsetvl/vlmax_call-3.c     |  207 ++
 .../gcc.target/riscv/rvv/vsetvl/vlmax_call-4.c     |   39 +
 .../riscv/rvv/vsetvl/vlmax_complex_loop-1.c        |   52 +
 .../riscv/rvv/vsetvl/vlmax_complex_loop-2.c        |   56 +
 .../gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c |   23 +
 .../riscv/rvv/vsetvl/vlmax_conflict-10.c           |   27 +
 .../riscv/rvv/vsetvl/vlmax_conflict-11.c           |   24 +
 .../riscv/rvv/vsetvl/vlmax_conflict-12.c           |   39 +
 .../gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.c |   23 +
 .../gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c |   30 +
 .../gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c |   29 +
 .../gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c |   32 +
 .../gcc.target/riscv/rvv/vsetvl/vlmax_conflict-6.c |   26 +
 .../gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c |   26 +
 .../gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.c |   27 +
 .../gcc.target/riscv/rvv/vsetvl/vlmax_conflict-9.c |   27 +
 .../riscv/rvv/vsetvl/vlmax_miss_default-1.c        |   32 +
 .../riscv/rvv/vsetvl/vlmax_miss_default-10.c       |   32 +
 .../riscv/rvv/vsetvl/vlmax_miss_default-11.c       |   32 +
 .../riscv/rvv/vsetvl/vlmax_miss_default-12.c       |   32 +
 .../riscv/rvv/vsetvl/vlmax_miss_default-13.c       |   32 +
 .../riscv/rvv/vsetvl/vlmax_miss_default-14.c       |  189 ++
 .../riscv/rvv/vsetvl/vlmax_miss_default-15.c       |   38 +
 .../riscv/rvv/vsetvl/vlmax_miss_default-16.c       |   38 +
 .../riscv/rvv/vsetvl/vlmax_miss_default-17.c       |   38 +
 .../riscv/rvv/vsetvl/vlmax_miss_default-18.c       |   38 +
 .../riscv/rvv/vsetvl/vlmax_miss_default-19.c       |   38 +
 .../riscv/rvv/vsetvl/vlmax_miss_default-2.c        |   32 +
 .../riscv/rvv/vsetvl/vlmax_miss_default-20.c       |   38 +
 .../riscv/rvv/vsetvl/vlmax_miss_default-21.c       |   38 +
 .../riscv/rvv/vsetvl/vlmax_miss_default-22.c       |   38 +
 .../riscv/rvv/vsetvl/vlmax_miss_default-23.c       |   38 +
 .../riscv/rvv/vsetvl/vlmax_miss_default-24.c       |   38 +
 .../riscv/rvv/vsetvl/vlmax_miss_default-25.c       |   38 +
 .../riscv/rvv/vsetvl/vlmax_miss_default-26.c       |   38 +
 .../riscv/rvv/vsetvl/vlmax_miss_default-27.c       |   38 +
 .../riscv/rvv/vsetvl/vlmax_miss_default-28.c       |  231 ++
 .../riscv/rvv/vsetvl/vlmax_miss_default-3.c        |   32 +
 .../riscv/rvv/vsetvl/vlmax_miss_default-4.c        |   32 +
 .../riscv/rvv/vsetvl/vlmax_miss_default-5.c        |   32 +
 .../riscv/rvv/vsetvl/vlmax_miss_default-6.c        |   32 +
 .../riscv/rvv/vsetvl/vlmax_miss_default-7.c        |   32 +
 .../riscv/rvv/vsetvl/vlmax_miss_default-8.c        |   32 +
 .../riscv/rvv/vsetvl/vlmax_miss_default-9.c        |   32 +
 .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c      |   37 +
 .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c     |   37 +
 .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c     |   37 +
 .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c     |   37 +
 .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c     |   37 +
 .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c     |  217 ++
 .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c     |   40 +
 .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c     |   40 +
 .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c     |   40 +
 .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c     |   40 +
 .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c     |   40 +
 .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c      |   37 +
 .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c     |   40 +
 .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c     |   40 +
 .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c     |   40 +
 .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c     |   40 +
 .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c     |   40 +
 .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c     |   40 +
 .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c     |   40 +
 .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c     |   40 +
 .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c     |  237 ++
 .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c      |   37 +
 .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c      |   37 +
 .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c      |   37 +
 .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c      |   37 +
 .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c      |   37 +
 .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c      |   37 +
 .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c      |   37 +
 .../riscv/rvv/vsetvl/vlmax_single_block-1.c        |  154 ++
 .../riscv/rvv/vsetvl/vlmax_single_block-10.c       |  143 ++
 .../riscv/rvv/vsetvl/vlmax_single_block-11.c       |   34 +
 .../riscv/rvv/vsetvl/vlmax_single_block-12.c       |   92 +
 .../riscv/rvv/vsetvl/vlmax_single_block-13.c       |   89 +
 .../riscv/rvv/vsetvl/vlmax_single_block-14.c       |   16 +
 .../riscv/rvv/vsetvl/vlmax_single_block-15.c       |   42 +
 .../riscv/rvv/vsetvl/vlmax_single_block-16.c       |  147 ++
 .../riscv/rvv/vsetvl/vlmax_single_block-17.c       |   32 +
 .../riscv/rvv/vsetvl/vlmax_single_block-18.c       |   32 +
 .../riscv/rvv/vsetvl/vlmax_single_block-19.c       |  105 +
 .../riscv/rvv/vsetvl/vlmax_single_block-2.c        |   70 +
 .../riscv/rvv/vsetvl/vlmax_single_block-3.c        |   70 +
 .../riscv/rvv/vsetvl/vlmax_single_block-4.c        |   49 +
 .../riscv/rvv/vsetvl/vlmax_single_block-5.c        |   49 +
 .../riscv/rvv/vsetvl/vlmax_single_block-6.c        |   28 +
 .../riscv/rvv/vsetvl/vlmax_single_block-7.c        |   28 +
 .../riscv/rvv/vsetvl/vlmax_single_block-8.c        |   28 +
 .../riscv/rvv/vsetvl/vlmax_single_block-9.c        |  147 ++
 .../riscv/rvv/vsetvl/vlmax_single_vtype-1.c        |   86 +
 .../riscv/rvv/vsetvl/vlmax_single_vtype-2.c        |   42 +
 .../riscv/rvv/vsetvl/vlmax_single_vtype-3.c        |   38 +
 .../riscv/rvv/vsetvl/vlmax_single_vtype-4.c        |   31 +
 .../riscv/rvv/vsetvl/vlmax_single_vtype-5.c        |   31 +
 .../riscv/rvv/vsetvl/vlmax_single_vtype-6.c        |   18 +
 .../riscv/rvv/vsetvl/vlmax_single_vtype-7.c        |   18 +
 .../riscv/rvv/vsetvl/vlmax_single_vtype-8.c        |   18 +
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-1.c        |   26 +
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-10.c       |   47 +
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-11.c       |   55 +
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-12.c       |   55 +
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-13.c       |   17 +
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-14.c       |   39 +
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-15.c       |   52 +
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-16.c       |   60 +
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-2.c        |   26 +
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-3.c        |   25 +
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-4.c        |   20 +
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-5.c        |   20 +
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-6.c        |   33 +
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-7.c        |   43 +
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-8.c        |   45 +
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-9.c        |   45 +
 216 files changed, 17616 insertions(+), 369 deletions(-)
 create mode 100644 gcc/config/riscv/riscv-vsetvl.cc
 create mode 100644 gcc/config/riscv/riscv-vsetvl.h
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/dump-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-11.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-12.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-13.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-24.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-34.c
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[Tcwg-commits] [gcc] branch master updated (6e85f89a7d5 -> 8577356f4b8)