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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-next-allyesconfig in repository toolchain/ci/gcc.
from 02f7334ac93 c++: Fix up handling of captured vars in lambdas in OpenMP [...] adds f5389e17e4b Update include/plugin-api.h. adds c8429c2aba8 API extension for binutils (type of symbols). adds f22712bd8a2 Fix inliner ICE on alias with flatten attribute [PR92372] adds 37482edc3f7 d/dmd: Merge upstream dmd d1a606599 adds 9def91e9f2a c: Fix up cfun->function_end_locus from the C FE [PR94029] adds f7dceb4e658 Fix cgraph_node::function_symbol availability compuattion [ [...] adds 3373d3e38ea Daily bump. adds 94e2418780f c++: Avoid unnecessary empty class copy [94175]. adds 4a18f168f47 [rs6000] Rewrite the declaration of a variable adds 05009698eeb gcc, Arm: Fix no_cond issue introduced by MVE adds 4119cd693d2 store-merging: Fix up -fnon-call-exceptions handling [PR94224] adds 0efe7d8796e gcc, Arm: Fix MVE move from GPR -> GPR adds 005f6fc59e5 gcc, Arm: Fix testisms for MVE testsuite adds 719c864225e gcc, Arm: Revert changes to {get,set}_fpscr adds 8fefa21fcf6 tree-optimization/94266 - fix object type extraction heuristics adds 7d4549b2cd2 Fix correct offset in ipa_get_jf_ancestor_result. adds 3eff57aacfe [ARM][GCC][6x]:MVE ACLE vaddq intrinsics using arithmetic p [...] adds 85a94e87901 [ARM][GCC][7x]: MVE vreinterpretq and vuninitializedq intrinsics. adds 92f80065d10 [ARM][GCC][1/8x]: MVE ACLE vidup, vddup, viwdup and vdwdup [...] adds 41e1a7ffae9 [ARM][GCC][2/8x]: MVE ACLE gather load and scatter store in [...] adds 3d42842c07f fix CTOR vectorization adds 261014a1be4 [ARM][GCC][9x]: MVE ACLE predicated intrinsics with (dont-c [...] adds 828878c35c8 c++: Include the constraint parameter mapping in diagnostic [...] adds c3562f81042 [ARM][GCC][10x]: MVE ACLE intrinsics "add with carry across [...] adds 1aa22b1916a c-family: Tighten vector handling in type_for_mode [PR94072] adds b5446d0cc09 d: Fix SEGV in hash_table<odr_name_hasher, false, xcallocat [...] adds 1dfcc3b541c [ARM][GCC][11x]: MVE ACLE vector interleaving store and dei [...] adds a23eff1bd04 c++: Add testcases from PR c++/69694 adds a89349e664f adjust SLP tree dumping adds 72b3bc895f0 Fix verifier ICE on wrong comdat local flag [PR93347] adds 68dd57808f7 rs6000: Add command line and builtin compatibility check adds cc3afc9db07 Regenerate gcc.pot. adds 29f23ed79b6 sra: Cap number of sub-access propagations with a param (PR 93435) adds 8416602026d Daily bump. adds 15711e837b2 Fix comma at end of enumerator list seen with -std=c++98. adds 497498c878d lra: Tighten check for reloading paradoxical subregs [PR94052]
No new revisions were added by this update.
Summary of changes: gcc/ChangeLog | 1586 ++ gcc/DATESTAMP | 2 +- gcc/c-family/ChangeLog | 7 + gcc/c-family/c-common.c | 11 +- gcc/c/ChangeLog | 14 + gcc/c/c-decl.c | 4 +- gcc/c/c-parser.c | 51 +- gcc/c/c-tree.h | 2 +- gcc/cgraph.c | 90 +- gcc/cgraph.h | 17 +- gcc/cgraphunit.c | 8 + gcc/config/arm/arm-builtins.c | 86 + gcc/config/arm/arm.md | 8 +- gcc/config/arm/arm_mve.h | 8413 ++++++++-- gcc/config/arm/arm_mve_builtins.def | 61 + gcc/config/arm/iterators.md | 8 + gcc/config/arm/mve.md | 1250 +- gcc/config/arm/neon.md | 32 +- gcc/config/arm/unspecs.md | 4 +- gcc/config/arm/vec-common.md | 42 +- gcc/config/arm/vfp.md | 7 +- gcc/config/rs6000/rs6000-internal.h | 1 - gcc/config/rs6000/rs6000.c | 9 +- gcc/config/rs6000/rs6000.h | 1 + gcc/cp/ChangeLog | 21 + gcc/cp/call.c | 4 + gcc/cp/cp-gimplify.c | 13 +- gcc/cp/cp-tree.h | 1 + gcc/cp/cxx-pretty-print.c | 18 +- gcc/cp/cxx-pretty-print.h | 1 + gcc/cp/error.c | 35 +- gcc/d/ChangeLog | 13 + gcc/d/d-tree.h | 5 + gcc/d/decl.cc | 10 +- gcc/d/dmd/MERGE | 2 +- gcc/d/dmd/dclass.c | 1 - gcc/d/dmd/expressionsem.c | 1 + gcc/d/dmd/module.h | 1 + gcc/d/types.cc | 48 + gcc/gimple-ssa-sprintf.c | 4 +- gcc/gimple-ssa-store-merging.c | 4 +- gcc/ipa-cp.c | 5 +- gcc/ipa-fnsummary.c | 4 - gcc/ipa-inline-transform.c | 9 +- gcc/ipa-inline.c | 3 + gcc/ipa-split.c | 2 +- gcc/lra-constraints.c | 24 +- gcc/lto-section-in.c | 1 + gcc/lto-streamer-out.c | 82 +- gcc/lto-streamer.h | 1 + gcc/params.opt | 4 + gcc/po/ChangeLog | 4 + gcc/po/gcc.pot | 15239 +++++++++++-------- gcc/symtab.c | 11 + gcc/testsuite/ChangeLog | 636 + gcc/testsuite/g++.dg/abi/empty30.C | 14 + gcc/testsuite/g++.dg/concepts/diagnostic6.C | 14 + gcc/testsuite/g++.dg/cpp0x/decltype74.C | 30 + gcc/testsuite/g++.dg/cpp0x/decltype75.C | 24 + gcc/testsuite/g++.dg/torture/pr93347.C | 306 + gcc/testsuite/g++.dg/torture/pr94202.C | 22 + gcc/testsuite/g++.dg/tree-ssa/pr94224.C | 34 + gcc/testsuite/g++.target/aarch64/pr94052.C | 174 + gcc/testsuite/gcc.c-torture/pr92372.c | 16 + gcc/testsuite/gcc.dg/attr-flatten-1.c | 18 + gcc/testsuite/gcc.dg/tree-ssa/pr93435.c | 159 + gcc/testsuite/gcc.misc-tests/gcov-pr94029.c | 14 + gcc/testsuite/gcc.target/aarch64/pr94072.c | 9 + .../gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c | 2 +- .../gcc.target/arm/mve/intrinsics/mve_fpu1.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fpu2.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fpu3.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_libcall1.c | 1 + .../gcc.target/arm/mve/intrinsics/mve_libcall2.c | 1 + .../arm/mve/intrinsics/mve_move_gpr_to_gpr.c | 18 + .../arm/mve/intrinsics/mve_vector_float.c | 3 +- .../arm/mve/intrinsics/mve_vector_float1.c | 3 +- .../arm/mve/intrinsics/mve_vector_float2.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_vector_int.c | 3 +- .../arm/mve/intrinsics/mve_vector_int1.c | 11 +- .../arm/mve/intrinsics/mve_vector_int2.c | 3 +- .../arm/mve/intrinsics/mve_vector_uint.c | 3 +- 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| 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot270_x_s16.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot270_x_s32.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot270_x_s8.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot90_x_s16.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot90_x_s32.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot90_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c | 23 + 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24 + .../arm/mve/intrinsics/vidupq_x_wb_u16.c | 26 + .../arm/mve/intrinsics/vidupq_x_wb_u32.c | 26 + .../gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c | 26 + .../arm/mve/intrinsics/viwdupq_m_n_u16.c | 24 + .../arm/mve/intrinsics/viwdupq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c | 24 + .../arm/mve/intrinsics/viwdupq_m_wb_u16.c | 24 + .../arm/mve/intrinsics/viwdupq_m_wb_u32.c | 24 + .../arm/mve/intrinsics/viwdupq_m_wb_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c | 22 + .../arm/mve/intrinsics/viwdupq_x_n_u16.c | 24 + .../arm/mve/intrinsics/viwdupq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c | 24 + .../arm/mve/intrinsics/viwdupq_x_wb_u16.c | 24 + .../arm/mve/intrinsics/viwdupq_x_wb_u32.c | 24 + .../arm/mve/intrinsics/viwdupq_x_wb_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vld1q_z_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_z_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_z_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_z_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_z_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_z_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_z_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_z_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vld2q_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_u8.c | 23 + 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| 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c | 15 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c | 15 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c | 15 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c | 15 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vnegq_x_f16.c | 23 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