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from 3db9d208dd misc: Add support for Linux uio.h RWF_NOAPPEND flag new cb5d84f1f8 aarch64/fpu: Add vector variants of erf new bdb5705b7b aarch64/fpu: Add vector variants of cosh new b09fee1d21 aarch64/fpu: Add vector variants of acosh new 81406ea3c5 aarch64/fpu: Add vector variants of asinh new 8b67920528 aarch64/fpu: Add vector variants of atanh new eedbbca0bf aarch64/fpu: Add vector variants of sinh new 3d3a4fb8e4 aarch64/fpu: Add vector variants of tanh new 87cb1dfcd6 aarch64/fpu: Add vector variants of erfc
The 8 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.
Summary of changes: math/auto-libm-test-in | 2 +- math/auto-libm-test-out-tanh | 50 +- sysdeps/aarch64/fpu/Makefile | 19 +- sysdeps/aarch64/fpu/Versions | 42 + sysdeps/aarch64/fpu/acosh_advsimd.c | 67 + sysdeps/aarch64/fpu/acosh_sve.c | 51 + sysdeps/aarch64/fpu/acoshf_advsimd.c | 78 + sysdeps/aarch64/fpu/acoshf_sve.c | 49 + sysdeps/aarch64/fpu/advsimd_f32_protos.h | 8 + sysdeps/aarch64/fpu/asinh_advsimd.c | 171 + sysdeps/aarch64/fpu/asinh_sve.c | 150 + sysdeps/aarch64/fpu/asinhf_advsimd.c | 80 + sysdeps/aarch64/fpu/asinhf_sve.c | 56 + sysdeps/aarch64/fpu/atanh_advsimd.c | 64 + sysdeps/aarch64/fpu/atanh_sve.c | 59 + sysdeps/aarch64/fpu/atanhf_advsimd.c | 79 + sysdeps/aarch64/fpu/atanhf_sve.c | 54 + sysdeps/aarch64/fpu/bits/math-vector.h | 64 + sysdeps/aarch64/fpu/cosh_advsimd.c | 108 + sysdeps/aarch64/fpu/cosh_sve.c | 105 + sysdeps/aarch64/fpu/coshf_advsimd.c | 84 + sysdeps/aarch64/fpu/coshf_sve.c | 59 + sysdeps/aarch64/fpu/erf_advsimd.c | 161 + sysdeps/aarch64/fpu/erf_data.c | 800 +++++ sysdeps/aarch64/fpu/erf_sve.c | 115 + sysdeps/aarch64/fpu/erfc_advsimd.c | 201 ++ sysdeps/aarch64/fpu/erfc_data.c | 3519 ++++++++++++++++++++ sysdeps/aarch64/fpu/erfc_sve.c | 167 + sysdeps/aarch64/fpu/erfcf_advsimd.c | 170 + sysdeps/aarch64/fpu/erfcf_data.c | 676 ++++ sysdeps/aarch64/fpu/erfcf_sve.c | 113 + sysdeps/aarch64/fpu/erff_advsimd.c | 123 + sysdeps/aarch64/fpu/erff_data.c | 544 +++ sysdeps/aarch64/fpu/erff_sve.c | 93 + sysdeps/aarch64/fpu/sinh_advsimd.c | 121 + sysdeps/aarch64/fpu/sinh_sve.c | 107 + sysdeps/aarch64/fpu/sinhf_advsimd.c | 88 + sysdeps/aarch64/fpu/sinhf_sve.c | 67 + sysdeps/aarch64/fpu/sv_erf_data.c | 1570 +++++++++ sysdeps/aarch64/fpu/sv_erff_data.c | 1058 ++++++ sysdeps/aarch64/fpu/sv_expf_inline.h | 75 + .../fpu/{expm1f_sve.c => sv_expm1f_inline.h} | 67 +- sysdeps/aarch64/fpu/sv_log1p_inline.h | 109 + sysdeps/aarch64/fpu/sv_log1pf_inline.h | 76 + sysdeps/aarch64/fpu/tanh_advsimd.c | 109 + sysdeps/aarch64/fpu/tanh_sve.c | 100 + sysdeps/aarch64/fpu/tanhf_advsimd.c | 76 + sysdeps/aarch64/fpu/tanhf_sve.c | 61 + sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c | 8 + sysdeps/aarch64/fpu/test-double-sve-wrappers.c | 8 + sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c | 8 + sysdeps/aarch64/fpu/test-float-sve-wrappers.c | 8 + sysdeps/aarch64/fpu/v_exp_tail_data.c | 110 + sysdeps/aarch64/fpu/v_expf_inline.h | 71 + sysdeps/aarch64/fpu/v_expm1f_inline.h | 73 + sysdeps/aarch64/fpu/v_log1p_inline.h | 103 + sysdeps/aarch64/fpu/v_log1pf_inline.h | 78 + sysdeps/aarch64/fpu/v_math.h | 10 + sysdeps/aarch64/fpu/vecmath_config.h | 46 + sysdeps/aarch64/libm-test-ulps | 64 + sysdeps/unix/sysv/linux/aarch64/libmvec.abilist | 40 + 61 files changed, 12423 insertions(+), 69 deletions(-) create mode 100644 sysdeps/aarch64/fpu/acosh_advsimd.c create mode 100644 sysdeps/aarch64/fpu/acosh_sve.c create mode 100644 sysdeps/aarch64/fpu/acoshf_advsimd.c create mode 100644 sysdeps/aarch64/fpu/acoshf_sve.c create mode 100644 sysdeps/aarch64/fpu/asinh_advsimd.c create mode 100644 sysdeps/aarch64/fpu/asinh_sve.c create mode 100644 sysdeps/aarch64/fpu/asinhf_advsimd.c create mode 100644 sysdeps/aarch64/fpu/asinhf_sve.c create mode 100644 sysdeps/aarch64/fpu/atanh_advsimd.c create mode 100644 sysdeps/aarch64/fpu/atanh_sve.c create mode 100644 sysdeps/aarch64/fpu/atanhf_advsimd.c create mode 100644 sysdeps/aarch64/fpu/atanhf_sve.c create mode 100644 sysdeps/aarch64/fpu/cosh_advsimd.c create mode 100644 sysdeps/aarch64/fpu/cosh_sve.c create mode 100644 sysdeps/aarch64/fpu/coshf_advsimd.c create mode 100644 sysdeps/aarch64/fpu/coshf_sve.c create mode 100644 sysdeps/aarch64/fpu/erf_advsimd.c create mode 100644 sysdeps/aarch64/fpu/erf_data.c create mode 100644 sysdeps/aarch64/fpu/erf_sve.c create mode 100644 sysdeps/aarch64/fpu/erfc_advsimd.c create mode 100644 sysdeps/aarch64/fpu/erfc_data.c create mode 100644 sysdeps/aarch64/fpu/erfc_sve.c create mode 100644 sysdeps/aarch64/fpu/erfcf_advsimd.c create mode 100644 sysdeps/aarch64/fpu/erfcf_data.c create mode 100644 sysdeps/aarch64/fpu/erfcf_sve.c create mode 100644 sysdeps/aarch64/fpu/erff_advsimd.c create mode 100644 sysdeps/aarch64/fpu/erff_data.c create mode 100644 sysdeps/aarch64/fpu/erff_sve.c create mode 100644 sysdeps/aarch64/fpu/sinh_advsimd.c create mode 100644 sysdeps/aarch64/fpu/sinh_sve.c create mode 100644 sysdeps/aarch64/fpu/sinhf_advsimd.c create mode 100644 sysdeps/aarch64/fpu/sinhf_sve.c create mode 100644 sysdeps/aarch64/fpu/sv_erf_data.c create mode 100644 sysdeps/aarch64/fpu/sv_erff_data.c create mode 100644 sysdeps/aarch64/fpu/sv_expf_inline.h copy sysdeps/aarch64/fpu/{expm1f_sve.c => sv_expm1f_inline.h} (59%) create mode 100644 sysdeps/aarch64/fpu/sv_log1p_inline.h create mode 100644 sysdeps/aarch64/fpu/sv_log1pf_inline.h create mode 100644 sysdeps/aarch64/fpu/tanh_advsimd.c create mode 100644 sysdeps/aarch64/fpu/tanh_sve.c create mode 100644 sysdeps/aarch64/fpu/tanhf_advsimd.c create mode 100644 sysdeps/aarch64/fpu/tanhf_sve.c create mode 100644 sysdeps/aarch64/fpu/v_exp_tail_data.c create mode 100644 sysdeps/aarch64/fpu/v_expf_inline.h create mode 100644 sysdeps/aarch64/fpu/v_expm1f_inline.h create mode 100644 sysdeps/aarch64/fpu/v_log1p_inline.h create mode 100644 sysdeps/aarch64/fpu/v_log1pf_inline.h