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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-defconfig in repository toolchain/ci/llvm-project.
from 56da41393df [SDAG] reduce code duplication in getNegatedExpression(); NFCI adds cd34c0570b5 [ORC] Bail out early if a replacement MaterializationUnit i [...] adds a7b8393ffea [ORC] Don't waste time building empty replacement Materiali [...] adds eb918d8daf1 [ORC] Use finer-grained and session locking in MachOPlatfor [...] adds ad2da631bf3 [ORC] Fix indentation in debugging output. adds 54aec178dac [ORC] Don't use a platform mutex for LLJIT's GenericLLVMIRP [...] adds 018dde4ce57 [AArch64][SVE] Add support for DestructiveBinaryImm Destruc [...] adds 9e2207a00bd [libc++] fix non-builtin is_void implementation adds a11e5b32dfb [InstCombine][X86] simplifyX86immShift - handle variable ou [...] adds c31ee83abb0 Add Builder::get{I32,I64}TensorAttr. adds 90308a4da16 [debugserver] Implement hardware breakpoints for ARM64 adds a983562b234 Precommit test for clang::CallGraph declared functions. adds c2586cab89f [InstCombine][X86] Tests for variable but in-range vector-b [...] adds 0cc2d237516 [Matrix] Hoist load/store generation logic, add helpers for [...] adds 430c9a80c17 [Hexagon] Enable linux #defines adds 30bb113beb3 [AMDGPU][NFC] Refactor emitEntryFunctionPrologue adds db099f994b5 [AMDGPU][NFC] Refactor some uses of unsigned to Register adds 60b1967c393 [AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descript [...] adds 0e9368cc8ca [AMDGPU] Move frame pointer from s34 to s33 adds b20ab412bf8 Teach TreeTransform to substitute into resolved TemplateArguments. adds e23d7865269 [JumpThreading] Fix infinite loop (PR44611) adds 796fb2e4749 [Matrix] Move multiply-add code generation into separate fu [...] adds c985b244ee1 [MSan] Simulate OOM in mmap_interceptor() adds 1db8b341a66 [Matrix] Fold single-use variable into assert adds b4f02d89e5d [AST] Make Expr::setDependence protected and remove add/rem [...] adds b89202e842a [clangd] Do not trigger go-to-def textual fallback inside s [...] adds f87563661d6 [MC][ARM] add implicit immediate form for ldrsbt/ldrht/ldrsht adds 95b6f62efb1 [InstSimplify] Add some vector shift tests to show lack of [...] adds 8a8778f25f1 [CMake] Enable the use of -ffile-prefix-map adds 98223f7931f [Fuchsia] Use -ffile-prefix-map adds d6fc61b7e8b [profile] Record the profile size as a property of the VMO adds 39253a50f0f [ORC] Re-apply 98f2bb44610, enable JITEventListeners in Orc [...] adds 6bc775a1fc1 [MLIR] Interfaces need to used add_mlir_library adds c999084619a [GlobalISel] Port some basic shufflevector undef combines f [...] adds 98ff6eb679c Cleanup the plumbing for DILineInfoSpecifier. [NFC] adds 678da7b109f AMDGPU/GlobalISel: Remove leftover #if 0 adds a3f974f3c33 [WebAssembly] SIMD bitmask intrinsics and builtin functions adds 6343526d640 Revert "Cleanup the plumbing for DILineInfoSpecifier. [NFC]" adds 34db3c3a184 [WebAssembly] SIMD integer abs instructions adds 08670d435bb [WebAssembly] Support swiftself and swifterror for WebAssem [...] adds 09ac859c136 [ELF][test] Make tests less address sensitive and delete re [...] adds 1c153774961 Recommit: CFGDiff: Simplify/common the begin/end implementa [...] adds f7d4bd81443 [MLIR] Fix for out-of-tree builds from install area. adds 4e6c778eca4 [XRay] Record the XRay data size as a property of the VMO adds 011b785505b [ELF] Create readonly PT_LOAD in the presence of a SECTIONS [...] adds 6ef1f3718f3 [sanitizer_coverage][Fuchsia] Set ZX_PROP_VMO_CONTENT_SIZE adds 0ddd04391d2 [MLIR] Fix op folding to not run pre-replace when not const [...] adds fc3752665f4 [RISCV] Passing small data limitation value to RISCV backend adds 032251e34d1 [Coroutines] Fix PR45130 adds a035726e5aa Revert "Generate Callee Saved Register (CSR) related cfi di [...] adds 728b878de68 [AMDGPU] Set the CostPerUse value for vgpr registers. adds 2cbb8c946a6 [AMDGPU] Reuse register during frame index elimination adds 3a8372ed02a [DSE] Support traversing MemoryPhis. adds be86bc76f0c [Matrix] Generalize ColumnMatrixTy to MatrixTy (NFC). adds e9630630ffa [Syntax] Split syntax tests adds 5c10967157d [InstCombine] Don't replace musttail result based on known bits adds 9cf920e64d1 [ARM] Extra MVE float loop tests. NFC adds 03727687766 [InstCombine] Simplify calls with "returned" attribute adds ebb04e9ca93 [NFC][RISCV] Test for 0.0 fp immediate adds 3c24aee7ee8 [RISCV] Select +0.0 immediate using fmv.{w,d}.x / fcvt.d.w adds b3499f572d3 [ARM] Change VDUP type to i32 for MVE adds baa6f6a7828 Revert "[TableGen][GlobalISel] Account for HwMode in Regist [...] adds 180581cfcf5 [clang] Add support for consteval constructors adds 467c4902a10 [lldb] Enable now passing part of TestDataFormatterStdString.py adds 63778bc653a [llvm-readobj][llvm-readelf][test] - Add a test to check ho [...] adds 089cfe113da Improve step over performance adds fd7300f717c [Syntax] Test both the default and windows target platforms [...] adds 86b093d1a18 [llvm-readobj] Allow syms from all sections to match stack [...] adds a09ff56b5b5 [Tests] Regenerate some test checks; NFC adds c1efdbcbe0d [ValueTracking] Add computeKnownBits DemandedElts support t [...] adds 9967352a034 Revert "[Syntax] Test both the default and windows target p [...] adds ce6c95aacae [InstCombine] Move test to instcombine; NFC adds fcba7c3534f [OPENMP50]Initial support for scan directive. adds 7f764fa18f6 [ValueTracking] Add some initial isKnownNonZero DemandedElt [...] adds a4edea29be2 Fix `-Wunused-variable` warning. NFC. adds ece6cf0fa56 [DSE,MSSA] Precommit additional tests for D73763. adds 7a85e3585ec [ARM,CDE] Implement GPR CDE intrinsics adds d22e6617125 [ARM,CDE] Implement CDE S and D-register intrinsics adds 969034b8603 [ARM,CDE] Implement CDE unpredicated Q-register intrinsics adds 6ae3eff8baa [ARM,CDE] Implement CDE vreinterpret intrinsics adds 6e34e71869a [AMDGPU] Enable divergence driven ISel for ADD/SUB i64 adds f8352502a35 [scudo][standalone] Allow fallback to secondary if primary is full adds 53d6b156bbb AMDGPU: Add more tests for fshr adds a950e3beefd AMDGPU: Move towards deprecating alignbit intrinsic adds d168b777803 [DAGCombiner] Fix non-determinism problem related to argume [...] adds fc902cb6e2b [PowerPC][AIX][NFC] Add zero-sized by val params to cc test. adds 94061df6e5f [analyzer] StdLibraryFunctionsChecker: Add argument constraints adds eddede9d518 [Syntax] Test both the default and windows target platforms [...] adds 45a9945b9ea [ARM,MVE] Add ACLE intrinsics for the vminv/vmaxv family. adds 1adfa4c9916 [ARM,MVE] Add ACLE intrinsics for the vaddv/vaddlv family. adds 34659de5fdd [InstCombine][X86] simplifyX86immShift - convert variable i [...] adds ffcc076a2b2 [[Clang CallGraph]] CallGraph should still record calls to decls. adds ce5173c0e17 Use FinishThunk to finish musttail thunks adds 32fbea15485 [X86] Prevent (bitcast (broadcast_load)) combine from produ [...] adds 56122fcd641 [PowerPC][AIX][NFC] Extend the test coverage of ByVal args. adds edcfb47ff6d [DAGCombiner] Do not fold truncate(build_vector(..)) if it [...] adds ededa65d559 [analyzer] StdLibraryFunctionsChecker: Add NotNull Arg Constraint adds f59bb40e361 Attempt to fix failing build-bot with [-Werror,-Wcovered-sw [...] new 942afe0cb2a [mlir/quant] fix a small typo in the quant utility new 0b18b568e91 [lldb-vscode] Don't use SBLaunchInfo in request_attach new 3205d1a8603 [InstCombine] Handle known shl nsw sign bit in SimplifyDemanded new 5de4ba1770f Cleanup the plumbing for DILineInfoSpecifier. [NFC - Try 2]
The 4 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.
Summary of changes: clang-tools-extra/clangd/XRefs.cpp | 12 + clang-tools-extra/clangd/unittests/XRefsTests.cpp | 5 +- clang/cmake/caches/Fuchsia-stage2.cmake | 2 +- clang/docs/ClangCommandLineReference.rst | 6 +- clang/include/clang-c/Index.h | 6 +- clang/include/clang/AST/Expr.h | 28 +- clang/include/clang/AST/RecursiveASTVisitor.h | 3 + clang/include/clang/AST/StmtOpenMP.h | 57 + clang/include/clang/Analysis/CallGraph.h | 5 + clang/include/clang/Basic/BuiltinsWebAssembly.def | 4 + clang/include/clang/Basic/CodeGenOptions.def | 3 + clang/include/clang/Basic/DiagnosticDriverKinds.td | 3 + clang/include/clang/Basic/DiagnosticSemaKinds.td | 9 +- clang/include/clang/Basic/StmtNodes.td | 1 + clang/include/clang/Basic/arm_cde.td | 159 +- clang/include/clang/Basic/arm_mve.td | 66 +- clang/include/clang/Driver/CC1Options.td | 2 + clang/include/clang/Driver/Options.td | 3 + clang/include/clang/Sema/Sema.h | 4 + clang/include/clang/Serialization/ASTBitCodes.h | 1 + .../clang/StaticAnalyzer/Checkers/Checkers.td | 7 + clang/lib/AST/ComputeDependence.cpp | 20 +- clang/lib/AST/Expr.cpp | 30 +- clang/lib/AST/ExprConcepts.cpp | 4 +- clang/lib/AST/StmtOpenMP.cpp | 21 + clang/lib/AST/StmtPrinter.cpp | 5 + clang/lib/AST/StmtProfile.cpp | 4 + clang/lib/Analysis/CallGraph.cpp | 6 +- clang/lib/Basic/OpenMPKinds.cpp | 13 + clang/lib/Basic/Targets.cpp | 3 + clang/lib/CodeGen/CGBuiltin.cpp | 8 + clang/lib/CodeGen/CGOpenMPRuntime.cpp | 5 + clang/lib/CodeGen/CGOpenMPRuntimeNVPTX.cpp | 4 + clang/lib/CodeGen/CGStmt.cpp | 3 + clang/lib/CodeGen/CGVTables.cpp | 5 +- clang/lib/CodeGen/CodeGenModule.cpp | 15 + clang/lib/CodeGen/CodeGenModule.h | 4 + clang/lib/Driver/ToolChains/Clang.cpp | 32 + clang/lib/Frontend/CompilerInvocation.cpp | 2 + clang/lib/Parse/ParseOpenMP.cpp | 2 + clang/lib/Sema/SemaDeclCXX.cpp | 14 +- clang/lib/Sema/SemaExceptionSpec.cpp | 1 + clang/lib/Sema/SemaExpr.cpp | 18 + clang/lib/Sema/SemaInit.cpp | 14 +- clang/lib/Sema/SemaOpenMP.cpp | 36 +- clang/lib/Sema/SemaOverload.cpp | 2 +- clang/lib/Sema/TreeTransform.h | 112 +- clang/lib/Serialization/ASTReaderStmt.cpp | 12 + clang/lib/Serialization/ASTWriterStmt.cpp | 7 + .../Checkers/StdLibraryFunctionsChecker.cpp | 218 +- clang/lib/StaticAnalyzer/Core/ExprEngine.cpp | 1 + clang/test/Analysis/analyzer-enabled-checkers.c | 1 + clang/test/Analysis/debug-CallGraph.cpp | 21 +- .../std-c-library-functions-arg-constraints.c | 87 + clang/test/Analysis/std-c-library-functions.c | 39 +- clang/test/CodeGen/arm-cde-gpr.c | 146 +- clang/test/CodeGen/arm-cde-reinterpret.c | 78 + clang/test/CodeGen/arm-cde-vec.c | 104 + clang/test/CodeGen/arm-cde-vfp.c | 145 ++ clang/test/CodeGen/arm-mve-intrinsics/vaddv.c | 470 ++++ clang/test/CodeGen/arm-mve-intrinsics/vminvq.c | 832 ++++++- clang/test/CodeGen/builtins-wasm.c | 18 + clang/test/CodeGen/riscv-sdata-module-flag.c | 48 + clang/test/CodeGenCXX/ms-thunks-ehspec.cpp | 27 + clang/test/CodeGenCXX/thunks-ehspec.cpp | 29 + clang/test/Driver/riscv-sdata-warning.c | 8 + clang/test/OpenMP/nesting_of_regions.cpp | 374 ++- clang/test/OpenMP/scan_ast_print.cpp | 50 + clang/test/OpenMP/scan_messages.cpp | 164 ++ clang/test/Preprocessor/hexagon-predefines.c | 12 + clang/test/Sema/arm-cde-immediates.c | 135 +- clang/test/SemaCXX/cxx2a-consteval.cpp | 144 +- clang/test/SemaTemplate/subst-into-subst.cpp | 34 + clang/tools/libclang/CIndex.cpp | 7 + clang/tools/libclang/CXCursor.cpp | 3 + clang/unittests/Tooling/Syntax/TreeTest.cpp | 763 +++--- clang/utils/TableGen/MveEmitter.cpp | 45 +- compiler-rt/lib/msan/msan_interceptors.cpp | 17 +- .../lib/profile/InstrProfilingPlatformFuchsia.c | 5 + .../sanitizer_coverage_fuchsia.cpp | 25 +- compiler-rt/lib/scudo/standalone/combined.h | 21 +- .../lib/scudo/standalone/tests/combined_test.cpp | 31 +- compiler-rt/lib/xray/xray_utils.cpp | 4 + libcxx/include/type_traits | 2 +- lld/ELF/ScriptParser.cpp | 6 - lld/test/ELF/arm-force-pi-thunk.s | 2 +- lld/test/ELF/arm-thumb-thunk-v6m.s | 4 +- lld/test/ELF/arm-thunk-linkerscript-dotexpr.s | 2 +- lld/test/ELF/arm-thunk-linkerscript.s | 2 +- lld/test/ELF/linkerscript/absolute-expr.test | 2 +- lld/test/ELF/linkerscript/align-empty.test | 8 +- lld/test/ELF/linkerscript/at-self-reference.s | 63 - lld/test/ELF/linkerscript/at.s | 9 +- lld/test/ELF/linkerscript/at4.s | 5 +- lld/test/ELF/linkerscript/common-assign.s | 8 +- lld/test/ELF/linkerscript/double-bss.test | 6 +- lld/test/ELF/linkerscript/extend-pt-load1.test | 6 +- lld/test/ELF/linkerscript/extend-pt-load2.test | 9 +- lld/test/ELF/linkerscript/extend-pt-load3.test | 7 +- lld/test/ELF/linkerscript/loadaddr.s | 2 +- lld/test/ELF/linkerscript/map-file2.test | 8 +- lld/test/ELF/linkerscript/merge-header-load.s | 5 +- lld/test/ELF/linkerscript/merge-sections-syms.s | 34 +- lld/test/ELF/linkerscript/merge-sections.s | 2 +- lld/test/ELF/linkerscript/noload.s | 53 +- lld/test/ELF/linkerscript/non-alloc.s | 6 +- lld/test/ELF/linkerscript/orphan-align.s | 2 +- lld/test/ELF/linkerscript/overlapping-sections.s | 12 +- lld/test/ELF/linkerscript/overlay.test | 5 +- lld/test/ELF/linkerscript/repsection-symbol.s | 8 +- lld/test/ELF/linkerscript/rosegment.test | 25 +- lld/test/ELF/linkerscript/sections-keep.s | 12 +- lld/test/ELF/linkerscript/sizeofheaders.s | 4 +- lld/test/ELF/linkerscript/symbol-conflict.s | 11 - lld/test/ELF/linkerscript/synthetic-symbols1.test | 18 +- lld/test/ELF/many-alloc-sections.s | 2 +- .../Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp | 2 +- lldb/source/Target/ThreadPlanStepOverRange.cpp | 4 + .../libstdcpp/string/TestDataFormatterStdString.py | 3 +- .../source/MacOSX/arm64/DNBArchImplARM64.cpp | 132 + .../source/MacOSX/arm64/DNBArchImplARM64.h | 15 +- lldb/tools/lldb-vscode/lldb-vscode.cpp | 3 - llvm/cmake/modules/HandleLLVMOptions.cmake | 18 +- llvm/cmake/modules/LLVMExternalProjectUtils.cmake | 1 + llvm/docs/AMDGPUUsage.rst | 220 +- llvm/docs/CMake.rst | 8 + llvm/examples/OrcV2Examples/CMakeLists.txt | 3 +- .../CMakeLists.txt | 16 + .../LLJITWithGDBRegistrationListener.cpp | 109 + llvm/include/llvm/Analysis/ValueTracking.h | 25 + .../llvm/CodeGen/GlobalISel/CombinerHelper.h | 7 + .../include/llvm/CodeGen/GlobalISel/RegisterBank.h | 13 +- .../llvm/CodeGen/GlobalISel/RegisterBankInfo.h | 3 +- llvm/include/llvm/DebugInfo/DIContext.h | 8 +- llvm/include/llvm/DebugInfo/Symbolize/DIPrinter.h | 8 +- .../llvm/DebugInfo/Symbolize/SymbolizableModule.h | 5 +- llvm/include/llvm/DebugInfo/Symbolize/Symbolize.h | 2 + .../llvm/ExecutionEngine/Orc/MachOPlatform.h | 5 +- .../ExecutionEngine/Orc/RTDyldObjectLinkingLayer.h | 19 +- llvm/include/llvm/ExecutionEngine/RuntimeDyld.h | 27 +- llvm/include/llvm/Frontend/OpenMP/OMPKinds.def | 1 + llvm/include/llvm/IR/CFGDiff.h | 76 +- llvm/include/llvm/IR/IntrinsicsARM.td | 92 +- llvm/include/llvm/IR/IntrinsicsWebAssembly.td | 4 + llvm/include/llvm/Target/GlobalISel/Combine.td | 25 +- llvm/lib/Analysis/ValueTracking.cpp | 120 +- llvm/lib/CodeGen/CFIInstrInserter.cpp | 76 +- llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp | 13 + llvm/lib/CodeGen/GlobalISel/RegisterBank.cpp | 8 +- llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp | 5 +- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 16 +- llvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp | 6 +- llvm/lib/DebugInfo/Symbolize/DIPrinter.cpp | 2 - .../DebugInfo/Symbolize/SymbolizableObjectFile.cpp | 22 +- .../DebugInfo/Symbolize/SymbolizableObjectFile.h | 4 +- llvm/lib/DebugInfo/Symbolize/Symbolize.cpp | 8 +- .../ExecutionEngine/Orc/CompileOnDemandLayer.cpp | 10 +- llvm/lib/ExecutionEngine/Orc/Core.cpp | 15 +- llvm/lib/ExecutionEngine/Orc/LLJIT.cpp | 73 +- llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp | 18 +- .../Orc/RTDyldObjectLinkingLayer.cpp | 70 +- .../ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp | 48 +- .../ExecutionEngine/RuntimeDyld/RuntimeDyldImpl.h | 8 +- .../Target/AArch64/AArch64ExpandPseudoInsts.cpp | 5 + llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 31 +- llvm/lib/Target/AArch64/SVEInstrFormats.td | 86 +- llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp | 2 - llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 28 +- .../Target/AMDGPU/AMDGPUInstructionSelector.cpp | 41 +- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 4 +- llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 13 +- .../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp | 1 - llvm/lib/Target/AMDGPU/SIFoldOperands.cpp | 17 +- llvm/lib/Target/AMDGPU/SIFrameLowering.cpp | 358 +-- llvm/lib/Target/AMDGPU/SIFrameLowering.h | 35 +- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 96 +- llvm/lib/Target/AMDGPU/SIInstructions.td | 1 - llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp | 24 +- llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h | 95 +- llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 137 +- llvm/lib/Target/AMDGPU/SIRegisterInfo.h | 5 - llvm/lib/Target/AMDGPU/SIRegisterInfo.td | 8 +- llvm/lib/Target/AMDGPU/VOP3Instructions.td | 2 +- llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp | 106 + llvm/lib/Target/ARM/ARMISelLowering.cpp | 90 +- llvm/lib/Target/ARM/ARMISelLowering.h | 16 +- llvm/lib/Target/ARM/ARMInstrCDE.td | 93 + llvm/lib/Target/ARM/ARMInstrInfo.td | 3 + llvm/lib/Target/ARM/ARMInstrMVE.td | 384 +-- llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 20 + llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 11 + llvm/lib/Target/RISCV/RISCVISelLowering.h | 2 + llvm/lib/Target/RISCV/RISCVInstrInfoD.td | 8 + llvm/lib/Target/RISCV/RISCVInstrInfoF.td | 6 + llvm/lib/Target/RISCV/RISCVRegisterBankInfo.cpp | 4 +- llvm/lib/Target/RISCV/RISCVRegisterBankInfo.h | 2 +- llvm/lib/Target/RISCV/RISCVSubtarget.cpp | 2 +- .../Target/WebAssembly/WebAssemblyAsmPrinter.cpp | 5 +- .../lib/Target/WebAssembly/WebAssemblyFastISel.cpp | 6 + .../WebAssembly/WebAssemblyFixFunctionBitcasts.cpp | 4 + .../Target/WebAssembly/WebAssemblyISelLowering.cpp | 52 +- .../lib/Target/WebAssembly/WebAssemblyInstrSIMD.td | 17 + .../Target/WebAssembly/WebAssemblyMCInstLower.cpp | 3 +- .../WebAssembly/WebAssemblyMachineFunctionInfo.cpp | 29 +- .../WebAssembly/WebAssemblyMachineFunctionInfo.h | 7 +- llvm/lib/Target/X86/X86FrameLowering.cpp | 31 +- llvm/lib/Target/X86/X86FrameLowering.h | 2 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 29 +- llvm/lib/Transforms/Coroutines/CoroSplit.cpp | 5 +- .../Transforms/InstCombine/InstCombineCalls.cpp | 44 +- .../InstCombine/InstCombineSimplifyDemanded.cpp | 14 + .../InstCombine/InstructionCombining.cpp | 13 +- .../lib/Transforms/Scalar/DeadStoreElimination.cpp | 163 +- llvm/lib/Transforms/Scalar/JumpThreading.cpp | 12 + .../Transforms/Scalar/LowerMatrixIntrinsics.cpp | 284 ++- .../Analysis/ValueTracking/knownnonzero-shift.ll | 6 +- .../GlobalISel/prelegalizercombiner-undef.mir | 58 + .../CodeGen/AArch64/dag-combine-trunc-build-vec.ll | 48 + .../AArch64/sve-intrinsics-shifts-merging.ll | 340 +++ .../AMDGPU/GlobalISel/divergent-control-flow.ll | 2 +- .../CodeGen/AMDGPU/GlobalISel/insertelement.ll | 4 +- .../AMDGPU/GlobalISel/inst-select-load-local.mir | 278 ++- .../AMDGPU/GlobalISel/inst-select-load-private.mir | 111 +- .../AMDGPU/GlobalISel/inst-select-store-local.mir | 224 +- .../GlobalISel/inst-select-store-private.mir | 383 ++- llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll | 20 +- llvm/test/CodeGen/AMDGPU/addrspacecast.ll | 4 +- llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll | 20 +- llvm/test/CodeGen/AMDGPU/amdhsa-trap-num-sgprs.ll | 4 +- llvm/test/CodeGen/AMDGPU/array-ptr-calc-i32.ll | 4 +- llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll | 10 +- llvm/test/CodeGen/AMDGPU/bypass-div.ll | 36 +- llvm/test/CodeGen/AMDGPU/byval-frame-setup.ll | 350 --- llvm/test/CodeGen/AMDGPU/call-argument-types.ll | 74 +- llvm/test/CodeGen/AMDGPU/call-constant.ll | 6 +- .../CodeGen/AMDGPU/call-graph-register-usage.ll | 18 +- .../CodeGen/AMDGPU/call-preserved-registers.ll | 45 +- llvm/test/CodeGen/AMDGPU/call-waitcnt.ll | 37 +- llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll | 94 +- .../AMDGPU/callee-special-input-sgprs-fixed-abi.ll | 3 +- .../CodeGen/AMDGPU/callee-special-input-sgprs.ll | 44 +- .../CodeGen/AMDGPU/callee-special-input-vgprs.ll | 50 +- llvm/test/CodeGen/AMDGPU/captured-frame-index.ll | 36 +- llvm/test/CodeGen/AMDGPU/cc-update.ll | 422 ++++ llvm/test/CodeGen/AMDGPU/cgp-addressing-modes.ll | 12 +- llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll | 28 +- llvm/test/CodeGen/AMDGPU/collapse-endcf.ll | 2 +- .../CodeGen/AMDGPU/control-flow-fastregalloc.ll | 64 +- .../AMDGPU/cross-block-use-is-not-abi-copy.ll | 38 +- llvm/test/CodeGen/AMDGPU/extload-private.ll | 8 +- .../AMDGPU/fast-unaligned-load-store.private.ll | 77 +- llvm/test/CodeGen/AMDGPU/fold-fi-mubuf.mir | 197 +- .../test/CodeGen/AMDGPU/frame-index-elimination.ll | 73 +- .../AMDGPU/frame-lowering-entry-all-sgpr-used.mir | 1 - .../CodeGen/AMDGPU/frame-lowering-fp-adjusted.mir | 3 +- llvm/test/CodeGen/AMDGPU/fshr.ll | 870 ++++++- llvm/test/CodeGen/AMDGPU/function-returns.ll | 202 +- .../AMDGPU/hsa-metadata-kernel-code-props-v3.ll | 8 +- .../AMDGPU/hsa-metadata-kernel-code-props.ll | 6 +- llvm/test/CodeGen/AMDGPU/idot8s.ll | 2277 ++++++++--------- llvm/test/CodeGen/AMDGPU/idot8u.ll | 2572 ++++++++++---------- .../CodeGen/AMDGPU/indirect-addressing-term.ll | 104 +- llvm/test/CodeGen/AMDGPU/indirect-call.ll | 14 +- llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll | 48 +- llvm/test/CodeGen/AMDGPU/ipra.ll | 2 +- llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll | 4 +- llvm/test/CodeGen/AMDGPU/large-alloca-graphics.ll | 42 +- .../AMDGPU/llvm.amdgcn.implicit.buffer.ptr.ll | 4 +- llvm/test/CodeGen/AMDGPU/load-hi16.ll | 20 +- llvm/test/CodeGen/AMDGPU/load-lo16.ll | 36 +- llvm/test/CodeGen/AMDGPU/memory-legalizer-load.ll | 8 +- llvm/test/CodeGen/AMDGPU/memory-legalizer-store.ll | 8 +- llvm/test/CodeGen/AMDGPU/memory_clause.ll | 93 +- llvm/test/CodeGen/AMDGPU/mesa3d.ll | 2 +- llvm/test/CodeGen/AMDGPU/mir-print-dead-csr-fi.mir | 1 - llvm/test/CodeGen/AMDGPU/misched-killflags.mir | 1 - llvm/test/CodeGen/AMDGPU/mubuf-offset-private.ll | 38 +- llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll | 34 +- llvm/test/CodeGen/AMDGPU/nested-calls.ll | 10 +- .../AMDGPU/optimize-exec-masking-pre-ra.mir | 1 - .../CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll | 341 ++- .../CodeGen/AMDGPU/pei-reg-scavenger-position.mir | 14 +- .../CodeGen/AMDGPU/pei-scavenge-sgpr-carry-out.mir | 23 +- .../test/CodeGen/AMDGPU/pei-scavenge-sgpr-gfx9.mir | 7 +- llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr.mir | 3 - .../CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir | 60 + .../CodeGen/AMDGPU/private-access-no-objects.ll | 14 +- llvm/test/CodeGen/AMDGPU/private-element-size.ll | 224 +- .../rename-independent-subregs-mac-operands.mir | 2 - ...hed-assert-dead-def-subreg-use-other-subreg.mir | 1 - ...d-handleMoveUp-subreg-def-across-subreg-def.mir | 1 - llvm/test/CodeGen/AMDGPU/scratch-buffer.ll | 14 +- llvm/test/CodeGen/AMDGPU/scratch-simple.ll | 49 +- llvm/test/CodeGen/AMDGPU/sdiv64.ll | 14 +- .../CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir | 25 +- llvm/test/CodeGen/AMDGPU/shl_add_ptr.ll | 12 +- llvm/test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll | 3 +- llvm/test/CodeGen/AMDGPU/sibling-call.ll | 22 +- .../test/CodeGen/AMDGPU/sp-too-many-input-sgprs.ll | 102 - llvm/test/CodeGen/AMDGPU/spill-agpr.ll | 16 +- llvm/test/CodeGen/AMDGPU/spill-before-exec.mir | 11 +- .../CodeGen/AMDGPU/spill-csr-frame-ptr-reg-copy.ll | 6 +- .../CodeGen/AMDGPU/spill-empty-live-interval.mir | 2 - llvm/test/CodeGen/AMDGPU/spill-m0.ll | 4 +- .../CodeGen/AMDGPU/spill-offset-calculation.ll | 45 +- llvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr.ll | 2 +- llvm/test/CodeGen/AMDGPU/srem64.ll | 14 +- .../stack-pointer-offset-relative-frameindex.ll | 21 +- llvm/test/CodeGen/AMDGPU/stack-realign-kernel.ll | 36 +- llvm/test/CodeGen/AMDGPU/stack-realign.ll | 58 +- .../AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir | 7 +- llvm/test/CodeGen/AMDGPU/store-hi16.ll | 28 +- .../CodeGen/AMDGPU/subreg-split-live-in-error.mir | 1 - llvm/test/CodeGen/AMDGPU/subvector-test.mir | 1 - llvm/test/CodeGen/AMDGPU/udiv64.ll | 12 +- llvm/test/CodeGen/AMDGPU/urem64.ll | 10 +- .../AMDGPU/vgpr-spill-emergency-stack-slot.ll | 6 +- .../AMDGPU/virtregrewrite-undef-identity-copy.mir | 1 - llvm/test/CodeGen/AMDGPU/wave32.ll | 6 +- llvm/test/CodeGen/AMDGPU/wqm.ll | 4 +- llvm/test/CodeGen/AMDGPU/wwm-reserved.ll | 8 +- .../MIR/AMDGPU/machine-function-info-no-ir.mir | 16 - .../CodeGen/MIR/AMDGPU/machine-function-info.ll | 18 +- .../mfi-parse-error-scratch-wave-offset-reg.mir | 12 - .../AMDGPU/mfi-scratch-wave-offset-reg-class.mir | 13 - .../MIR/AMDGPU/parse-order-reserved-regs.mir | 2 - llvm/test/CodeGen/PowerPC/aix-cc-byval.ll | 55 +- llvm/test/CodeGen/RISCV/double-arith.ll | 56 +- llvm/test/CodeGen/RISCV/float-arith.ll | 88 +- llvm/test/CodeGen/RISCV/float-br-fcmp.ll | 8 +- llvm/test/CodeGen/RISCV/fp-imm.ll | 116 + llvm/test/CodeGen/Thumb2/cde-gpr.ll | 189 ++ llvm/test/CodeGen/Thumb2/cde-vec.ll | 114 + llvm/test/CodeGen/Thumb2/cde-vfp.ll | 198 ++ llvm/test/CodeGen/Thumb2/mve-float16regloops.ll | 1491 ++++++++++++ llvm/test/CodeGen/Thumb2/mve-float32regloops.ll | 1418 +++++++++++ llvm/test/CodeGen/Thumb2/mve-fmas.ll | 10 +- llvm/test/CodeGen/Thumb2/mve-intrinsics/dup.ll | 8 +- llvm/test/CodeGen/Thumb2/mve-intrinsics/ternary.ll | 16 +- llvm/test/CodeGen/Thumb2/mve-intrinsics/vaddq.ll | 8 +- llvm/test/CodeGen/Thumb2/mve-intrinsics/vaddv.ll | 416 ++++ llvm/test/CodeGen/Thumb2/mve-intrinsics/vminvq.ll | 849 ++++++- llvm/test/CodeGen/Thumb2/mve-intrinsics/vmulq.ll | 6 +- llvm/test/CodeGen/Thumb2/mve-intrinsics/vsubq.ll | 8 +- llvm/test/CodeGen/Thumb2/mve-pred-threshold.ll | 14 +- llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll | 56 +- llvm/test/CodeGen/Thumb2/mve-vdup.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-vldst4.ll | 2 +- llvm/test/CodeGen/WebAssembly/simd-arith.ll | 36 + llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll | 30 + llvm/test/CodeGen/WebAssembly/swiftcc.ll | 46 + llvm/test/CodeGen/X86/cfi-epilogue-with-return.mir | 48 - .../CodeGen/X86/cfi-epilogue-without-return.mir | 53 - .../X86/cfi-inserter-callee-save-register.mir | 34 - .../X86/cfi-inserter-verify-inconsistent-csr.mir | 28 - llvm/test/CodeGen/X86/fdiv.ll | 24 + llvm/test/DebugInfo/AMDGPU/variable-locations.ll | 2 +- llvm/test/MC/ARM/arm-memory-instructions.s | 6 + llvm/test/MC/WebAssembly/simd-encodings.s | 18 + llvm/test/Transforms/Coroutines/no-suspend.ll | 52 + .../MSSA/memset-unknown-sizes.ll | 71 + .../MSSA/multiblock-exceptions.ll | 1 - .../DeadStoreElimination/MSSA/multiblock-loops.ll | 39 +- .../MSSA/multiblock-memoryphis.ll | 41 +- .../MSSA/multiblock-multipath.ll | 76 + .../MSSA/multiblock-overlap.ll | 112 + .../DeadStoreElimination/MSSA/multiblock-simple.ll | 105 +- llvm/test/Transforms/GVN/PRE/volatile.ll | 143 +- .../InstCombine/X86/x86-vector-shifts.ll | 108 + llvm/test/Transforms/InstCombine/align-attr.ll | 2 +- llvm/test/Transforms/InstCombine/call-returned.ll | 51 + .../Transforms/InstCombine/expensive-combines.ll | 2 +- .../test/Transforms/InstCombine/fortify-folding.ll | 4 +- .../InstCombine}/known-signbit-shift.ll | 17 +- llvm/test/Transforms/InstCombine/strcpy_chk-1.ll | 2 +- llvm/test/Transforms/InstCombine/strncpy_chk-1.ll | 2 +- llvm/test/Transforms/InstCombine/unused-nonnull.ll | 9 +- llvm/test/Transforms/InstSimplify/assume.ll | 6 +- llvm/test/Transforms/InstSimplify/call.ll | 4 + llvm/test/Transforms/InstSimplify/compare.ll | 42 + .../Transforms/InstSimplify/shift-knownbits.ll | 44 +- .../JumpThreading/PR44611-across-header-hang.ll | 22 + .../test/tools/llvm-readobj/ELF/reloc-addends.test | 155 ++ llvm/test/tools/llvm-readobj/ELF/stack-sizes.test | 73 +- llvm/tools/lli/lli.cpp | 6 + llvm/tools/llvm-readobj/ELFDumper.cpp | 30 +- llvm/tools/llvm-symbolizer/llvm-symbolizer.cpp | 5 +- .../DebugInfo/DWARF/DWARFDebugLineTest.cpp | 7 +- llvm/utils/TableGen/RegisterBankEmitter.cpp | 64 +- mlir/cmake/modules/MLIRConfig.cmake.in | 4 +- mlir/include/mlir/IR/Builders.h | 7 + mlir/lib/Dialect/Quant/Utils/UniformSupport.cpp | 4 +- mlir/lib/IR/Builders.cpp | 14 + mlir/lib/Interfaces/CMakeLists.txt | 12 +- mlir/lib/Transforms/Utils/FoldUtils.cpp | 14 +- 395 files changed, 19368 insertions(+), 7441 deletions(-) create mode 100644 clang/test/Analysis/std-c-library-functions-arg-constraints.c create mode 100644 clang/test/CodeGen/arm-cde-reinterpret.c create mode 100644 clang/test/CodeGen/arm-cde-vec.c create mode 100644 clang/test/CodeGen/arm-cde-vfp.c create mode 100644 clang/test/CodeGen/arm-mve-intrinsics/vaddv.c create mode 100644 clang/test/CodeGen/riscv-sdata-module-flag.c create mode 100644 clang/test/CodeGenCXX/ms-thunks-ehspec.cpp create mode 100644 clang/test/CodeGenCXX/thunks-ehspec.cpp create mode 100644 clang/test/Driver/riscv-sdata-warning.c create mode 100644 clang/test/OpenMP/scan_ast_print.cpp create mode 100644 clang/test/OpenMP/scan_messages.cpp create mode 100644 clang/test/SemaTemplate/subst-into-subst.cpp delete mode 100644 lld/test/ELF/linkerscript/at-self-reference.s delete mode 100644 lld/test/ELF/linkerscript/symbol-conflict.s create mode 100644 llvm/examples/OrcV2Examples/LLJITWithGDBRegistrationListener/CM [...] create mode 100644 llvm/examples/OrcV2Examples/LLJITWithGDBRegistrationListener/LL [...] create mode 100644 llvm/test/CodeGen/AArch64/dag-combine-trunc-build-vec.ll create mode 100644 llvm/test/CodeGen/AArch64/sve-intrinsics-shifts-merging.ll create mode 100644 llvm/test/CodeGen/AMDGPU/cc-update.ll create mode 100644 llvm/test/CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir delete mode 100644 llvm/test/CodeGen/AMDGPU/sp-too-many-input-sgprs.ll delete mode 100644 llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-wave-offse [...] delete mode 100644 llvm/test/CodeGen/MIR/AMDGPU/mfi-scratch-wave-offset-reg-class.mir create mode 100644 llvm/test/CodeGen/RISCV/fp-imm.ll create mode 100644 llvm/test/CodeGen/Thumb2/cde-gpr.ll create mode 100644 llvm/test/CodeGen/Thumb2/cde-vec.ll create mode 100644 llvm/test/CodeGen/Thumb2/cde-vfp.ll create mode 100644 llvm/test/CodeGen/Thumb2/mve-float16regloops.ll create mode 100644 llvm/test/CodeGen/Thumb2/mve-float32regloops.ll create mode 100644 llvm/test/CodeGen/Thumb2/mve-intrinsics/vaddv.ll create mode 100644 llvm/test/CodeGen/WebAssembly/swiftcc.ll delete mode 100644 llvm/test/CodeGen/X86/cfi-epilogue-with-return.mir delete mode 100644 llvm/test/CodeGen/X86/cfi-epilogue-without-return.mir delete mode 100644 llvm/test/CodeGen/X86/cfi-inserter-callee-save-register.mir delete mode 100644 llvm/test/CodeGen/X86/cfi-inserter-verify-inconsistent-csr.mir create mode 100644 llvm/test/Transforms/DeadStoreElimination/MSSA/memset-unknown-sizes.ll create mode 100644 llvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-multipath.ll create mode 100644 llvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-overlap.ll create mode 100644 llvm/test/Transforms/InstCombine/call-returned.ll rename llvm/test/{Analysis/ValueTracking => Transforms/InstCombine}/known-signbit- [...] create mode 100644 llvm/test/Transforms/JumpThreading/PR44611-across-header-hang.ll create mode 100644 llvm/test/tools/llvm-readobj/ELF/reloc-addends.test