[Tcwg-commits] [llvm] branch master updated (84a8da9431f -> 199c0d32e96)

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from 84a8da9431f AMDGPU: Consolidate SMRD TableGen patterns new 199c0d32e96 [RISCV] Compress addiw rd, x0, simm6 to c.li rd, simm6

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Summary of changes: lib/Target/RISCV/RISCVInstrInfoC.td | 2 ++ test/MC/RISCV/rv64c-aliases-valid.s | 20 ++++++++++---------- 2 files changed, 12 insertions(+), 10 deletions(-)